XC3S50 Datasheet, PDF (44/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 1.2V FPGA Family: Functional Description
Power-On
Set PROG_B Low
after Power-On
V_CCINT >1V
and V_CCAUX > 2V
No
and V_CCO Bank 4 > 1V
Yes
Clear configuration
memory
Yes _{PROG_B = Low}
No
No
INIT_ B = High?
Yes
Sample mode pins
Load configuration
data frames
CRC
No
correct?
Yes
Start-Up
sequence
User mode
INIT_B goes Low.
Abort Start-Up
No
Yes
Reconfigure?
DS099_26_041103
Figure 23: Configuration Flow Diagram for the Serial and Parallel Modes
DS099-2 (v1.2) July 11, 2003
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