XC3S50 Datasheet, PDF (153/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: Pinout Descriptions
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Table 30: FG676 Package Pinout (Continued)
XC3S1000
Bank Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
FG676
Pin
Number
Type
N/A VCCAUX
VCCAUX
VCCAUX
AF25 VCCAUX
N/A VCCAUX
VCCAUX
VCCAUX
B1 VCCAUX
N/A VCCAUX
VCCAUX
VCCAUX
B26 VCCAUX
N/A VCCAUX
VCCAUX
VCCAUX
J1 VCCAUX
N/A VCCAUX
VCCAUX
VCCAUX
J26 VCCAUX
N/A VCCAUX
VCCAUX
VCCAUX
V1 VCCAUX
N/A VCCAUX
VCCAUX
VCCAUX
V26 VCCAUX
N/A VCCINT
VCCINT
VCCINT
H8 VCCINT
N/A VCCINT
VCCINT
VCCINT
H19 VCCINT
N/A VCCINT
VCCINT
VCCINT
J9 VCCINT
N/A VCCINT
VCCINT
VCCINT
J10 VCCINT
N/A VCCINT
VCCINT
VCCINT
J17 VCCINT
N/A VCCINT
VCCINT
VCCINT
J18 VCCINT
N/A VCCINT
VCCINT
VCCINT
K9 VCCINT
N/A VCCINT
VCCINT
VCCINT
K10 VCCINT
N/A VCCINT
VCCINT
VCCINT
K17 VCCINT
N/A VCCINT
VCCINT
VCCINT
K18 VCCINT
N/A VCCINT
VCCINT
VCCINT
U9 VCCINT
N/A VCCINT
VCCINT
VCCINT
U10 VCCINT
N/A VCCINT
VCCINT
VCCINT
U17 VCCINT
N/A VCCINT
VCCINT
VCCINT
U18 VCCINT
N/A VCCINT
VCCINT
VCCINT
V9 VCCINT
N/A VCCINT
VCCINT
VCCINT
V10 VCCINT
N/A VCCINT
VCCINT
VCCINT
V17 VCCINT
N/A VCCINT
VCCINT
VCCINT
V18 VCCINT
N/A VCCINT
VCCINT
VCCINT
W8 VCCINT
N/A VCCINT
VCCINT
VCCINT
W19 VCCINT
VCC CCLK
AUX
CCLK
CCLK
AD26 CONFIG
Table 30: FG676 Package Pinout (Continued)
XC3S1000
Bank Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
FG676
Pin
Number
Type
VCC DONE
AUX
DONE
DONE
AC24 CONFIG
VCC HSWAP_EN
AUX
VCC M0
AUX
VCC M1
AUX
HSWAP_EN
M0
M1
HSWAP_EN
M0
M1
C2 CONFIG
AE3 CONFIG
AC3 CONFIG
VCC M2
AUX
VCC PROG_B
AUX
M2
PROG_B
M2
PROG_B
AF3 CONFIG
D3 CONFIG
VCC TCK
AUX
TCK
TCK
B24
JTAG
VCC TDI
AUX
VCC TDO
AUX
TDI
TDO
TDI
TDO
C1
JTAG
D24
JTAG
VCC TMS
AUX
TMS
TMS
A24
JTAG
User I/Os by Bank
Table 31 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks for the XC3S1000 in
the FG676 package. Similarly, Table 32 shows how the
available user-I/O pins are distributed between the eight I/O
banks for the XC3S1500 in the FG676 package. Finally,
Table 33 shows the same information for the XC3S2000 in
the FG676 package.
Table 31: User I/Os Per Bank for XC3S1000 in FG676 Package
Edge
I/O
Maximum
Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
49
40
0
2
5
Top
1
50
41
0
2
5
2
48
41
0
2
5
Right
3
48
41
0
2
5
4
50
35
6
2
5
Bottom
5
50
35
6
2
5
6
48
41
0
2
5
Left
7
48
41
0
2
5
GCLK
2
2
0
0
2
2
0
0
66
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