XC3S50 Datasheet, PDF (9/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 1.2V FPGA Family: Functional Description
R
T
TFF1
T1
D
Q
CE
CK
SR REV
DDR
MUX
TCE
T2
D
Q
TFF2
CE
CK
SR REV
Three-state Path
O1
OTCLK1
OCE
O2
OTCLK2
OFF1
D
Q
CE
CK
SR REV
DDR
MUX
D
Q
OFF2
CE
CK
SR REV
Program-
mable
Output
DCI
Driver
Output Path
VCCO
Weak
Pull-Up
Weak
Pull-
Down
ESD
I/O
Pin
ESD
Weak
Keeper
Latch
IQ1
I
ICLK1
ICE
IQ2
ICLK2
SR
REV
2
40
D
Q
IFF1
CE
CK
SR REV
Fixed
Delay
D
Q
IFF2
CE
CK
SR REV
LVCMOS, LVTTL, PCI
Single-ended Standards
using VREF
Differential Standards
VREF
Pin
I/O Pin
from
Adjacent
IOB
Input Path
Note: All IOB signals communicating with the FPGA's internal logic have the option of inverting polarity.
Figure 1: Simplified IOB Diagram
DS099_01_040703
www.xilinx.com
1-800-255-7778
DS099-2 (v1.2) July 11, 2003
Advance Product Specification