XC3S50 Datasheet, PDF (42/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Spartan-3 1.2V FPGA Family: Functional Description
D[0:7]
CCLK
RDWR_B
BUSY
2.5V
2.5V
CS_B
2.5V
4.7KΩ
4.7KΩ
V_CCO Banks 4 & 5
V_CCAUX V_CCINT
1.2V
Spartan-3
Slave
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
PROG_B
2.5V
M1
M2
M0
DONE INIT_B
GND
CS_B
V_CCO Banks 4 & 5
V_CCAUX V_CCINT
1.2V
Spartan-3
Slave
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
PROG_B
2.5V
M1
M2
M0
DONE INIT_B
GND
DONE
INIT_B
Notes:
PROG_B
DS099_24_041103
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA
to be configured in the chain shown above (or for the single FPGA as may be the case). This enables the DONE pin to drive
High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining FPGAs in the chain. Second,
DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain and require the pull-up resistor shown in
grey. In most cases, a value between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE synchronously with a long
chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise
time within one clock cycle.
2. If the FPGAs use different configuration data files, configure them in sequence by first asserting the CS_B of one FPGA then
asserting the CS_B of the other FPGA.
3. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration Interface.
Figure 21: Connection Diagram for Slave Parallel Configuration
DS099-2 (v1.2) July 11, 2003
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