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R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 18: Timing for the IOB Three-State Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Max
Max
Units
Synchronous Output Enable/Disable Times
T_IOCKHZ
Time from the active transition at LVCMOS25, 12mA
2.32
2.66
ns
the OTCLK input of the
output drive, Fast
Three-state Flip-Flop (TFF) to slew rate
when the Output pin enters the
high-impedance state
T_IOCKON(2)
Time from the active transition at
TFF’s OTCLK input to when the
Output pin drives valid data
3.78
4.34
ns
Asynchronous Output Enable/Disable Times
T_GTS
Time from asserting the Global LVCMOS25, 12mA
7.03
8.08
ns
Three State net (GTS) net to
output drive, Fast
when the Output pin enters the slew rate
high-impedance state
Set/Reset Times
T_IOSRHZ
Time from asserting TFF’s SR LVCMOS25, 12mA
3.28
3.77
ns
input to when the Output pin
output drive, Fast
enters a high-impedance state slew rate
T_IOSRON(2)
Time from asserting TFF’s SR
input at TFF to when the Output
pin drives valid data
4.75
5.45
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set
forth in Table 5 and Table 8.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned
to the data Output. When this is true, add the appropriate Output adjustment from Table 19.
DS099-3 (v1.3) March 4, 2004
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