XC3S50 Datasheet, PDF (30/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Spartan-3 1.2V FPGA Family: Functional Description
BUFG
FPGA
CLK90
CLK180
CLKIN _CLK270
CLKDV
DCM _CLK2X
CLK2X180
CLKFB
CLK0
BUFGMUX
Clock
Net Delay
BUFGMUX
CLK0
(a) On-Chip with CLK0 Feedback
FPGA
IBUFG
IBUFG
CLK90
CLK180
CLKIN CLK270
CLKDV
DCM _CLK2X
CLK2X180
CLKFB
CLK0
OBUFG
OBUFG
Clock
Net Delay
BUFG
FPGA
CLK0
CLK90
CLKIN CLK180
CLK270
DCM CLKDV
CLK2X180
BUFGMUX
Clock
Net Delay
CLKFB
CLK2X
BUFGMUX
CLK2X
(b) On-Chip with CLK2X Feedback
FPGA
IBUFG
IBUFG
CLK0
CLK90
CLKIN CLK180
CLK270
DCM CLKDV
CLK2X180
OBUFG
CLKFB
CLK2X
OBUFG
Clock
Net Delay
CLK0
CLK2X
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_071003
Notes:
1. In the Low Frequency mode, all seven DLL outputs are available. In the High Frequency mode, only the CLK0, CLK180,
and CLKDV outputs are available.
Figure 15: Input Clock, Output Clock, and Feedback Connections for the DLL
In the on-chip synchronization case (Figure 15a and
Figure 15b), it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to
the FPGA’s internal registers. Either a Global Clock Buffer
(BUFG) or a BUFGMUX affords access to the global clock
network. As shown in Figure 15a, the feedback loop is cre-
ated by routing CLK0 (or CLK2X, in Figure 15b) to a global
clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case (Figure 15c and
Figure 15d), CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers
(OBUF) to drive an external clock network plus registers on
the board. As shown in Figure 15c, the feedback loop is
formed by feeding CLK0 (or CLK2X, in Figure 15d) back
into the FPGA using an IBUFG, which directly accesses the
global clock network, or an IBUF. Then, the global clock net
is connected directly to the CLKFB input.
DLL Frequency Modes
The DLL supports two distinct operating modes, High Fre-
quency and Low Frequency, with each specified over a differ-
ent clock frequency range. The DLL_FREQUENCY_MODE
attribute chooses between the two modes. When the
attribute is set to LOW, the Low Frequency mode permits all
seven DLL clock outputs to operate over a low-to-moderate
frequency range. When the attribute is set to HIGH, the High
Frequency mode allows the CLK0, CLK180 and CLKDV out-
puts to operate at the highest possible frequencies. The
remaining DLL clock outputs are not available for use in High
Frequency mode.
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it
exceeds the maximum permitted, divide it down to an
acceptable value using the CLKIN_DIVIDE_BY_2 attribute.
When this attribute is set to TRUE, the CLKIN frequency is
divided by a factor of two just as it enters the DCM.
Coarse Phase Shift Outputs of the DLL Compo-
nent
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180 and
CLK270 outputs for 90°, 180° and 270° phase-shifted sig-
nals, respectively. These signals are described in Table 12.
DS099-2 (v1.2) July 11, 2003
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Advance Product Specification
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