XC3S50 Datasheet, PDF (56/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Internal
Logic
Spartan-3 FPGA Family: DC and Switching Characteristics
V_OUTP
P
N
V_OUTN
Differential
I/O Pair Pins
V_OUTN
V_OUTP
GND level
50%
V_OCM
V_OD
V_OH
V_OL
V_OCM = Output common mode voltage =
V_OUTP + V_OUTN
2
V_OD = Output differential voltage = ^V_OUTP ^{- V}_OUTN
V_OH = Output voltage indicating a High logic level
V_OL ^{= Output voltage indicating a Low logic level} DS099-3_02_012304
Figure 2: Differential Output Voltages
Table 11: DC Characteristics of User I/Os Using Differential Signal Standards
Signal Standard
Device
Revision
Min
(mV)
V_OD
Typ
(mV)
Max
(mV)
∆V_OD
Min Max
(mV) (mV)
V_OCM
Min Typ
(V)
(V)
Max
(V)
∆V_OCM
Min Max
(mV) (mV)
V_OH
Min Max
(V) (V)
V_OL
Min Max
(V) (V)
LDT_25
All⁽³⁾ 430⁽⁴⁾ 600 670 –15 15 0.495 0.600 0.715 –15 15
-
-
-
-
LVDS_25
0⁽³⁾
100
-
600
-
-
0.80
-
1.6
-
-
-
-
-
-
Future 250
-
400
-
-
1.125
- 1.375 -
- 1.00 1.475 0.925 1.38
BLVDS_25
All
250 350 450
-
-
-
1.20
-
-
-
-
-
-
-
LVDSEXT_25
0⁽³⁾
100
-
600
-
-
0.80
-
1.6
-
-
-
-
-
-
Future 330
-
700
-
-
1.125
- 1.375 -
-
- 1.700 0.705 -
ULVDS_25
LVPECL_25⁽⁷⁾
All⁽³⁾
All
430 600 670
-
-
-
-
-
- 0.495 0.600 0.715 -
-
-
-
-
-
-
-
-
-
-
- 1.35 1.745 0.565 1.005
RSDS_25
0⁽³⁾
100
-
600
-
-
0.80
-
1.6
-
-
-
-
-
-
Future 100
-
400
-
-
1.1
-
1.4
-
-
-
-
-
-
Notes:
1. The numbers in this table are based on the conditions set forth in Table 5 and Table 10.
2. V_OD, ∆V_OD, and ∆V_OCM are differential measurements.
3. For this standard, to ensure that the FPGA’s output pair meets specifications, it is necessary to set the LVDSBIAS option in the BitGen utility, part of
the Xilinx development software. See XAPP751. The option settings for LVDS_25, LVDSEXT_25, and RSDS_25 are different from those for LDT_25
and ULVDS_25.
4. This value must be compatible with the receiver to which the FPGA’s output pair is connected.
5. Output voltage measurements for all differential standards are made with a termination resistor (R_T) of 100Ω across the N and P pins of the differential
signal pair.
6. At any given time, only one differential standard may be assigned to each bank.
7. Each LVPECL output-pair requires three external resistors: a 70Ω resistor in series with each output followed by a 240Ω shunt resistor. These are in
addition to the external 100Ω termination resistor at the receiver side. See Figure 3.
70Ω
240Ω
100Ω
70Ω
ds099-3_08_020304
Figure 3: External Terminations for LVPECL
DS099-3 (v1.3) March 4, 2004
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