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R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 16: Input Timing Adjustments for IOB
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
Add the
Adjustment Below
Speed Grade
-5
-4
Single-Ended Standards
GTL, GTL_DCI
–0.37
–0.37
GTLP, GTLP_DCI
–0.37
–0.37
HSTL_I, HSTL_I_DCI
–0.18
–0.18
HSTL_III, HSTL_III_DCI
–0.19
–0.19
HSTL_I_18,
HSTL_I_DCI_18
–0.26
–0.26
HSTL_II_18,
HSTL_II_DCI_18
–0.26
–0.26
HSTL_III_18,
HSTL_III_DCI_18
–0.20
–0.20
LVCMOS12
0.40
0.40
LVCMOS15, LVDCI_15,
LVDCI_DV2_15
0.47
0.47
LVCMOS18, LVDCI_18,
LVDCI_DV2_18
0.30
0.30
LVCMOS25, LVDCI_25,
0
0
LVDCI_DV2_25
LVCMOS33, LVDCI_33,
LVDCI_DV2_33
0.09
0.09
LVTTL
–0.31
–0.31
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 16: Input Timing Adjustments for IOB (Continued)
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
Add the
Adjustment Below
Speed Grade
-5
-4
Units
PCI33_3
0.32
0.32
ns
SSTL18_I, SSTL18_I_DCI
–0.17
–0.17
ns
SSTL2_I, SSTL2_I_DCI
–0.19
–0.19
ns
SSTL2_II, SSTL2_II_DCI
–0.21
–0.21
ns
Differential Standards
LDT_25
0.04
0.04
ns
LVDS_25, LVDS_25_DCI
0.06
0.06
ns
BLVDS_25
ns
LVDSEXT_25,
ns
LVDSEXT_25_DCI
ULVDS_25
–0.05
–0.05
ns
LVPECL_25
ns
RSDS_25
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 20 and are based on the operating
conditions set forth in Table 5, Table 8, and Table 10.
2. These adjustments are used to convert input path times
originally specified for the LVCMOS25 standard to times that
correspond to other signal standards.
DS099-3 (v1.3) March 4, 2004
www.xilinx.com
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