XC3S50 Datasheet, PDF (36/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Spartan-3 1.2V FPGA Family: Functional Description
Table 19: DCM STATUS Bus
Bit
Name
Description
0 Phase Shift
Overflow
A value of 1 indicates a phase shift overflow when one of two conditions occur:
• Incrementing (or decrementing) TPS beyond 255/256 of a CLKIN cycle.
• The DLL is producing its maximum possible phase shift (i.e., all delay taps are active).⁽¹⁾
1 CLKIN Activity A value of 1 indicates that the CLKIN signal is not toggling. A value of 0 indicates toggling. This
bit functions only when the CLKFB input is connected.⁽²⁾
2 Reserved
-
3 Reserved
-
4 Reserved
-
5 Reserved
-
6 Reserved
-
7 Reserved
-
Notes:
1. The DLL phase shift with all delay taps active is specified as the parameter FINE_SHIFT_RANGE.
2. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit will not go High when the CLKIN signal stops.
Table 20: Status Attributes
Attribute
Description
Values
STARTUP_WAIT Delays transition from configuration to user mode until lock condition is achieved. TRUE, FALSE
Stabilizing DCM Clocks Before User Mode
It is possible to delay the completion of device configuration
until after the DLL has achieved a lock condition using the
STARTUP_WAIT attribute described in Table 20. This
option ensures that the FPGA does not enter user mode —
i.e., begin functional operation — until all system clocks
generated by the DCM are stable. In order to achieve the
delay, it is necessary to set the attribute to TRUE as well as
set the BitGen option LCK_cycle to one of the six cycles
making up the Startup phase of configuration. The selected
cycle defines the point at which configuration will halt until
the LOCKED output goes High.
Global Clock Network
Spartan-3 devices have eight Global Clock inputs called
GCLK0 - GCLK7. These inputs provide access to a
low-capacitance, low-skew network that is well-suited to
carrying high-frequency signals. The Spartan-3 clock net-
work is shown in Figure 18. GCLK0 through GCLK3 are
placed at the center of the die’s bottom edge. GCLK4
through GCLK7 are placed at the center of the die’s top
edge. It is possible to route each of the eight Global Clock
inputs to any CLB on the die.
Eight Global Clock Multiplexers (also called BUFGMUX ele-
ments) are provided that accept signals from Global Clock
inputs and route them to the internal clock network as well
as DCMs. Four BUFGMUX elements are placed at the cen-
ter of the die’s bottom edge, just above the GCLK0 - GCLK4
inputs. The remaining four BUFGMUX elements are placed
at the center of the die’s top edge, just below the GCLK4 -
GCLK7 inputs.
Each BUFGMUX element is a 2-to-1 multiplexer that can
receive signals from any of the four following sources:
1. One of the four Global Clock inputs on the same side of
the die — top or bottom — as the BUFGMUX element in
use.
2. Any of four nearby horizontal Double lines.
3. Any of four outputs from the DCM in the right-hand
quadrant that is on the same side of the die as the
BUFGMUX element in use.
4. Any of four outputs from the DCM in the left-hand
quadrant that is on the same side of the die as the
BUFGMUX element in use.
Sources 3 and 4 are not available on the XC3S50 die that
lacks DCMs.
Each BUFGMUX can switch incoming clock signals to two
possible destinations:
1. The vertical spine belonging to the same side of the die
— top or bottom — as the BUFGMUX element in use.
The two spines — top and bottom — each comprise
four vertical clock lines, each running from one of the
DS099-2 (v1.2) July 11, 2003
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