XC3S50 Datasheet, PDF (154/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: Pinout Descriptions
Table 32: User I/Os Per Bank for XC3S1500 in FG676 Package
Edge
I/O
Maximum
Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
62
52
0
2
6
Top
1
61
51
0
2
6
2
60
52
0
2
6
Right
3
60
52
0
2
6
4
63
47
6
2
6
Bottom
5
61
45
6
2
6
6
60
52
0
2
6
Left
7
60
52
0
2
6
Table 33: User I/Os Per Bank for XC3S2000 in FG676 Package
Edge
Maximum
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
62
52
0
2
6
Top
1
61
51
0
2
6
2
61
53
0
2
6
Right
3
60
52
0
2
6
4
63
47
6
2
6
Bottom
5
61
45
6
2
6
6
61
53
0
2
6
Left
7
60
52
0
2
6
GCLK
2
2
0
0
2
2
0
0
GCLK
2
2
0
0
2
2
0
0
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
67
Product Specification
1-800-255-7778