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Spartan-3 FPGA Family: DC and Switching Characteristics
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Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital Fre-
quency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applica-
tions. All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables (Table 27 and Table 28) apply to any application that
only employs the DLL component. When the DFS and/or
the PS components are used together with the DLL, then
the specifications listed in the DFS and PS tables (Table 29
through Table 32) supersede any corresponding ones in the
DLL tables. DLL specifications that do not change with the
addition of DFS or PS functions are presented in Table 27
and Table 28.
Table 27: Recommended Operating Conditions for the DLL
Symbol
Description
Input Frequency Ranges
F_CLKIN CLKIN_FREQ_DLL_LF Frequency for the
CLKIN_FREQ_DLL_HF ^{CLKIN input}
Frequency
Mode/
F_CLKIN Range
Device
Revision
Speed Grade
-5
-4
Min Max Min Max
Units
Low
High
All
24⁽²⁾ 165⁽³⁾ 24 165⁽³⁾ MHz
0
48 280⁽³⁾ 48 280⁽³⁾ MHz
Future
48 326 48 TBD MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as
All
0
45% 55% 45% 55% -
a percentage of the
CLKIN period
F_CLKIN < 200 MHz Future
40% 60% 40% 60%
-
F_CLKIN > 200 MHz
45% 55% 45% 55% -
Input Clock Jitter and Delay Path Variation
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
Cycle-to-cycle jitter at
the CLKIN input
Low
High
All
-300 +300 -300 +300 ps
-150 +150 -150 +150 ps
CLKIN_CYC_PER_DLL_LF
CLKIN_CYC_PER_DLL_HF
Period jitter at the
CLKIN input
Low
High
-1
+1
-1
+1
ns
-1
+1
-1
+1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of
All
off-chip feedback delay
from the DCM output
to the CLKFB input
-1
+1
-1
+1
ns
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. Use of the DFS permits lower F_CLKIN frequencies. See Table 29.
3. To double the maximum effective F_CLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE.
28
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DS099-3 (v1.3) March 4, 2004
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Advance Product Specification