XC3S50 Datasheet, PDF(67/192 Page) Xilinx, Inc – Revolutionary 90-nanometer process technology

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XC3S50 Datasheet, PDF (67/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Spartan-3 FPGA Family: DC and Switching Characteristics

Timing Measurement Methodology

When measuring timing parameters at the programmable

I/Os, different signal standards call for different test condi-

tions. Table 20 presents the conditions to use for each stan-

dard.

The method for measuring Input timing is as follows: A sig-

nal that swings between a Low logic level of VL and a High

logic level of VH is applied to the Input under test. Some

standards also require the application of a bias voltage to

the VREF pins of a given bank to properly set the

input-switching threshold. The measurement point of the

Input signal (VM) is commonly located halfway between VL

and VH.

The Output test setup is shown in Figure 4. A termination

voltage VT is applied to the termination resistor RT, the other

end of which is connected to the Output. For each standard,

RT and VT generally take on the standard values recom-

mended for minimizing signal reflections. If the standard

does not ordinarily use terminations (e.g., LVCMOS,

LVTTL), then RT is set to 1Mâ¦ to indicate an open connec-

tion, and VT is set to zero. The same measurement point

(VM) that was used at the Input is also used at the Output.

VT (VREF)

FPGA Output

RT (RREF)

VM (VMEAS)

CL (CREF)

ds099-3_07_012004

Notes:

1. The names shown in parentheses are

used in the IBIS file.

Figure 4: Output Test Setup

Table 20: Test Methods for Timing Measurement at I/Os

Signal Standard

Single-Ended

GTL

GTL_DCI

GTLP

GTLP_DCI

HSTL_I

HSTL_I_DCI

HSTL_III

HSTL_III_DCI

HSTL_I_18

HSTL_I_DCI_18

HSTL_II_18

HSTL_II_DCI_18

HSTL_III_18

HSTL_III_DCI_18

LVCMOS12

LVCMOS15

LVDCI_15

LVDCI_DV2_15

VREF

(V)

0.8

1.0

0.75

0.90

1.1

Inputs

(V)

VREF - 0.2

VREF - 0.5

VREF + 0.2

VREF + 0.5

1.2

1.5

Outputs

(â¦)

(V)

1.2

1.5

0.75

1.5

0.9

1.8

Inputs and

Outputs

(V)

VREF

0.75

www.xilinx.com

DS099-3 (v1.3) March 4, 2004

1-800-255-7778

Advance Product Specification

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