XC3S50 Datasheet, PDF (20/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 1.2V FPGA Family: Functional Description
The aspect ratio — i.e., width vs. depth — of each block
RAM is configurable. Furthermore, multiple blocks can be
cascaded to create still wider and/or deeper memories.
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAM16_S[w_A]_S[w_B] calls out the dual-port primi-
tive, where the integers w_A and w_B specify the total data
path width at ports w_A and w_B, respectively. Thus, a
RAM16_S9_S18 is a dual-port RAM with a 9-bit-wide Port A
and an 18-bit-wide Port B. A name of the form RAM16_S[w]
identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port. A
RAM16_S18 is a single-port RAM with an 18-bit-wide port.
Other memory functions — e.g., FIFOs, data path width
conversion, ROM, etc. — are readily available using the
CORE Generator™ system, part of the Xilinx development
software.
Arrangement of RAM Blocks on Die
The XC3S50 has one column of block RAM. The Spartan-3
devices ranging from the XC3S200 to XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000
have four columns. The position of the columns on the die is
shown in Figure 1 in Module 1: Introduction and Ordering
Information. For a given device, the total available RAM
blocks are distributed equally among the columns. Table 8
shows the number of RAM blocks, the data storage capac-
ity, and the number of columns for each device.
Table 8: Number of RAM Blocks by Device
Device
Total Number
of RAM Blocks
Total
Addressable
Locations (bits)
XC3S50
4
73,728
XC3S200
12
221,184
XC3S400
16
294,912
XC3S1000
24
442,368
XC3S1500
32
589,824
XC3S2000
40
737,280
XC3S4000
96
1,769,472
XC3S5000
104
1,916,928
Number
of
Columns
1
2
2
2
2
2
4
4
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common RAM block, which has a maximum capacity of
18,432 bits — or 16,384 bits when no parity lines are used.
Each port has its own dedicated set of data, control and
clock lines for synchronous read and write operations.
There are four basic data paths, as shown in Figure 7: (1)
write to and read from Port A, (2) write to and read from Port
B, (3) data transfer from Port A to Port B, and (4) data trans-
fer from Port B to Port A.
Write
4 Read
Write
1
Read
Spartan-3
Dual Port
Block RAM
Read 3
Write
Write
2
Read
DS099-2_12_030703
Figure 7: Block RAM Data Paths
Block RAM Port Signal Definitions
Representations of the dual-port primitive
RAM16_S[w_A]_S[w_B] and the single-port primitive
RAM16_S[w] with their associated signals are shown in
Figure 8a and Figure 8b, respectively. These signals are
defined in Table 9.
DS099-2 (v1.2) July 11, 2003
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