XC3S50 Datasheet, PDF (134/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
User I/Os by Bank
Table 26 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks on the FG320 pack-
age.
Table 26: User I/Os Per Bank in FG320 Package
Maximum
Maximum LVDS
Package Edge I/O Bank
I/O
Pairs
I/O
0
26
11
19
Top
1
26
11
19
Right
2
29
14
23
3
29
14
23
4
27
11
13
Bottom
5
26
11
13
6
29
14
23
Left
7
29
14
23
Spartan-3 FPGA Family: Pinout Descriptions
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
3
0
2
3
0
2
4
0
2
4
6
2
4
6
2
3
0
2
4
0
2
4
GCLK
2
2
0
0
2
2
0
0
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
47
Product Specification
1-800-255-7778