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Spartan-3 1.2V FPGA Family: Functional Description
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Table 17: Signals for Variable Phase Mode
Signal
Direction
Description
PSEN⁽¹⁾
Input Enables PSCLK for variable phase adjustment.
PSCLK⁽¹⁾
Input Clock to synchronize phase shift adjustment.
PSINCDEC⁽¹⁾
Input
Chooses between increment and decrement for phase adjustment. It is synchronized to the
PSCLK signal.
PSDONE
Output
Goes High to indicate that present phase adjustment is complete and PS component is
ready for next phase adjustment request. It is synchronized to the PSCLK signal.
Notes:
1. It is possible to program this input for either a true or inverted polarity
The Variable Phase Mode
The “Variable Phase” mode dynamically adjusts the fine
phase shift over time using three inputs to the PS compo-
nent, namely PSEN, PSCLK and PSINCDEC, as defined in
Table 17.
Just following device configuration, the PS component ini-
tially determines T_PS by evaluating Equation (4) for the
value assigned to the PHASE_SHIFT attribute. Then to
dynamically adjust that phase shift, use the three PS inputs
to increase or decrease the fine phase shift.
PSINCDEC is synchronized to the PSCLK clock signal,
which is enabled by asserting PSEN. It is possible to drive
the PSCLK input with the CLKIN signal or any other clock
signal. A request for phase adjustment is entered as follows:
For each PSCLK cycle that PSINCDEC is High, the PS
component adds 1/256 of a CLKIN cycle to T_PS. Similarly,
for each enabled PSCLK cycle that PSINCDEC is Low, the
PS component subtracts 1/256 of a CLKIN cycle from T_PS.
The phase adjustment may require as many as 100 CLKIN
cycles plus three PSCLK cycles to take effect, at which
point the output PSDONE goes High for one PSCLK cycle.
This pulse indicates that the PS component has finished the
present adjustment and is now ready for the next request.
Asserting the Reset (RST) input, returns T_PS to its original
shift time, as determined by the PHASE_SHIFT attribute
value. The set of waveforms in Figure 17c illustrates the
relationship between CLKFB and CLKIN in the Variable
Phase mode.
The Status Logic Component
The Status Logic component not only reports on the state of
the DCM but also provides a means of resetting the DCM to
an initial known state. The signals associated with the Sta-
tus Logic component are described in Table 18.
As a rule, the Reset (RST) input is asserted only upon con-
figuring the device or changing the CLKIN frequency. A
DCM reset does not affect attribute values (e.g.,
CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST
must be tied to GND.
The eight bits of the STATUS bus are defined in Table 19.
Table 18: Status Logic Signals
Signal
Direction
Description
RST
Input
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay
of zero. Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0]
Output The bit values on the STATUS bus provide information regarding the state of DLL and PS
operation
LOCKED
Output Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals
are out-of-phase when Low.
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