XC3S50 Datasheet, PDF (116/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
User I/Os by Bank
Table 19 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks on the TQ144 pack-
age.
Table 19: User I/Os Per Bank in TQ144 Package
Maximum
Package Edge I/O Bank
I/O
I/O
0
10
5
Top
1
9
4
Right
2
14
10
3
15
11
4
11
0
Bottom
5
9
0
6
14
10
Left
7
15
11
Spartan-3 FPGA Family: Pinout Descriptions
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
1
0
2
1
0
2
2
0
2
2
6
2
1
6
0
1
0
2
2
0
2
2
GCLK
2
2
0
0
2
2
0
0
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
29
Product Specification
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