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Spartan-3 FPGA Family: Pinout Descriptions
Table 2: Spartan-3 Pin Definitions
Pin Name
Direction
I/O: General-purpose I/O pins
I/O
User-defined as input,
output, bidirectional,
three-state output,
open-drain output,
open-source output
I/O_Lxxy_#
User-defined as input,
output, bidirectional,
three-state output,
open-drain output,
open-source output
DUAL: Dual-purpose configuration pins
IO_Lxxy_#/DIN/D0,
IO_Lxxy_#/D1,
IO_Lxxy_#/D2,
IO_Lxxy_#/D3,
IO_Lxxy_#/D4,
IO_Lxxy_#/D5,
IO_Lxxy_#/D6,
IO_Lxxy_#/D7
Input during configuration
Possible bidirectional I/O
after configuration if
SelectMap port is retained.
Otherwise, user I/O after
configuration
IO_Lxxy_#/CS_B
Input during Parallel mode
configuration
Possible input after
configuration if SelectMap
port is retained.
Otherwise, user I/O after
configuration
IO_Lxxy_#/RDWR_B
Input during Parallel mode
configuration
Possible input after
configuration if SelectMap
port is retained.
Otherwise, user I/O after
configuration
IO_Lxxy_#/
BUSY/DOUT
Output during configuration
Possible output after
configuration if SelectMap
port is retained.
Otherwise, user I/O after
configuration
Description
User I/O:
Unrestricted single-ended user-I/O pin. Supports all I/O standards
except the differential standards.
User I/O, Half of Differential Pair:
Unrestricted single-ended user-I/O pin or half of a differential pair.
Supports all I/O standards including the differential standards.
Configuration Data Port:
In Parallel (SelectMAP) modes, D0-D7 are byte-wide configuration
data pins. These pins become user I/Os after configuration unless
the SelectMAP port is retained via the Persist bitstream option.
In Serial modes, DIN (D0) serves as the single configuration data
input. This pin becomes a user I/O after configuration unless
retained by the Persist bitstream option.
Chip Select for Parallel Mode Configuration:
In Parallel (SelectMAP) modes, this is the active-Low Chip Select
signal. This pin becomes a user I/O after configuration unless the
SelectMAP port is retained via the Persist bitstream option.
Read/Write Control for Parallel Mode Configuration:
In Parallel (SelectMAP) modes, this is the active-Low Write
Enable, active-High Read Enable signal. This pin becomes a user
I/O after configuration unless the SelectMAP port is retained via
the Persist bitstream option.
Configuration Data Rate Control for Parallel Mode, Serial Data
Output for Serial Mode:
In Parallel (SelectMAP) modes, BUSY throttles the rate at which
configuration data is loaded. This pin becomes a user I/O after
configuration unless the SelectMAP port is retained via the Persist
bitstream option.
In Serial modes, DOUT provides preamble and configuration data
to downstream devices in a multi-FPGA daisy-chain. This pin
becomes a user I/O after configuration.
DS099-4 (v1.5) July 13, 2004
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Product Specification
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