XC3S50 Datasheet, PDF (136/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Spartan-3 FPGA Family: Pinout Descriptions
FG456: 456-lead Fine-pitch Ball Grid
Array
The 456-lead fine-pitch ball grid array package, FG456,
supports three different Spartan-3 devices, including the
XC3S400, the XC3S1000, and the XC3S1500. The foot-
prints for the XC3S1000 and XC3S1500 are identical, as
shown in Table 27 and Figure 13. The XC3S400, however,
has fewer I/O pins which consequently results in 69 uncon-
nected pins on the FG456 package, labeled as “N.C.” In
Table 27 and Figure 13, these unconnected pins are indi-
cated with a black diamond symbol (‹).
All the package pins appear in Table 27 and are sorted by
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S400 pinout and the
pinout for the XC3S1000 and XC3S1500, then that differ-
ence is highlighted in Table 27. If the table entry is shaded
grey, then there is an unconnected pin on the XC3S400 that
maps to a user-I/O pin on the XC3S1000 and XC3S1500. If
the table entry is shaded tan, then the unconnected pin on
the XC3S400 maps to a VREF-type pin on the XC3S1000
and XC3S1500. If the other VREF pins in the bank all con-
nect to a voltage reference to support a special I/O stan-
dard, then also connect the N.C. pin on the XC3S400 to the
same VREF voltage. This provides maximum flexibility as
you could potentially migrate a design from the XC3S400
device to an XC3S1000 or XC3S1500 FPGA without chang-
ing the printed circuit board.
Pinout Table
Table 27: FG456 Package Pinout
Bank
3S400
Pin Name
3S1000
3S1500
Pin Name
0
IO
IO
0
IO
IO
0
IO
IO
0
IO
IO
0
IO/VREF_0 IO/VREF_0
0
IO/VREF_0 IO/VREF_0
0
N.C. (‹)
IO/VREF_0
0
IO/VREF_0 IO/VREF_0
0
IO_L01N_0/ IO_L01N_0/
VRP_0
VRP_0
0
IO_L01P_0/ IO_L01P_0/
VRN_0
VRN_0
0
IO_L06N_0 IO_L06N_0
0
IO_L06P_0 IO_L06P_0
0
IO_L09N_0 IO_L09N_0
0
IO_L09P_0 IO_L09P_0
FG456
Pin
Number
A10
D9
D10
F6
A3
C7
E5
F7
B4
A4
D5
C5
B5
A5
Type
I/O
I/O
I/O
I/O
VREF
VREF
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
Table 27: FG456 Package Pinout (Continued)
Bank
3S400
Pin Name
3S1000
3S1500
Pin Name
FG456
Pin
Number
0
IO_L10N_0 IO_L10N_0
E6
0
IO_L10P_0 IO_L10P_0
D6
0
IO_L15N_0 IO_L15N_0
C6
0
IO_L15P_0 IO_L15P_0
B6
0
IO_L16N_0 IO_L16N_0
E7
0
IO_L16P_0 IO_L16P_0
D7
0
N.C. (‹)
IO_L19N_0
B7
0
N.C. (‹)
IO_L19P_0
A7
0
N.C. (‹)
IO_L22N_0
E8
0
N.C. (‹)
IO_L22P_0
D8
0
IO_L24N_0 IO_L24N_0
B8
0
IO_L24P_0 IO_L24P_0
A8
0
IO_L25N_0 IO_L25N_0
F9
0
IO_L25P_0 IO_L25P_0
E9
0
IO_L27N_0 IO_L27N_0
B9
0
IO_L27P_0 IO_L27P_0
A9
0
IO_L28N_0 IO_L28N_0
F10
0
IO_L28P_0 IO_L28P_0
E10
0
IO_L29N_0 IO_L29N_0
C10
0
IO_L29P_0 IO_L29P_0
B10
0
IO_L30N_0 IO_L30N_0
F11
0
IO_L30P_0 IO_L30P_0
E11
0
IO_L31N_0 IO_L31N_0
D11
0
IO_L31P_0/ IO_L31P_0/
C11
VREF_0
VREF_0
0
IO_L32N_0/ IO_L32N_0/
B11
GCLK7
GCLK7
0
IO_L32P_0/ IO_L32P_0/
A11
GCLK6
GCLK6
0
VCCO_0
VCCO_0
C8
0
VCCO_0
VCCO_0
F8
0
VCCO_0
VCCO_0
G9
0
VCCO_0
VCCO_0
G10
0
VCCO_0
VCCO_0
G11
1
IO
IO
A12
1
IO
IO
E16
1
IO
IO
F12
1
IO
IO
F13
1
IO
IO
F16
1
IO
IO
F17
1
IO/VREF_1 IO/VREF_1
E13
1
N.C. (‹)
IO/VREF_1
F14
1
IO_L01N_1/ IO_L01N_1/
C19
VRP_1
VRP_1
1
IO_L01P_1/ IO_L01P_1/
B20
VRN_1
VRN_1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
I/O
I/O
I/O
I/O
I/O
VREF
VREF
DCI
DCI
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
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Product Specification
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