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Spartan-3 1.2V FPGA Family: Functional Description
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in Table 12. The clock outputs drive simulta-
neously; however, the High Frequency mode only supports
a subset of the outputs available in the Low Frequency
mode. See DLL Frequency Modes, page 23. Signals that
initialize and report the state of the DLL are discussed in
The Status Logic Component, page 28.
Table 12: DLL Signals
Signal Direction
Description
CLKIN
Input Accepts original clock signal.
CLKFB
Input
Accepts either CLK0 or CLK2X as feed back signal. (Set
CLK_FEEDBACK attribute accordingly).
CLK0
Output Generates clock signal with same frequency and phase as CLKIN.
CLK90
Output Generates clock signal with same frequency as CLKIN, only
phase-shifted 90°.
CLK180
Output Generates clock signal with same frequency as CLKIN, only
phase-shifted 180°.
CLK270
Output Generates clock signal with same frequency as CLKIN, only
phase-shifted 270°.
CLK2X
Output Generates clock signal with same phase as CLKIN, only twice the
frequency.
CLK2X180 Output Generates clock signal with twice the frequency of CLKIN,
phase-shifted 180° with respect to CLKIN.
CLKDV
Output Divides the CLKIN frequency by CLKDV_DIVIDE value to generate
lower frequency clock signal that is phase-aligned to CLKIN.
Mode Support
Low
High
Frequency Frequency
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
Yes
The clock signal supplied to the CLKIN input serves as a
reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock
skew, the common approach to using the DLL is as follows:
The CLK0 signal is passed through the clock distribution
network to all the registers it synchronizes. These registers
are either internal or external to the FPGA. After passing
through the clock distribution network, the clock signal
returns to the DLL via a feedback line called CLKFB. The
control block inside the DLL measures the phase error
between CLKFB and CLKIN. This phase error is a measure
of the clock skew that the clock distribution network intro-
duces. The control block activates the appropriate number
of delay elements to cancel out the clock skew. Once the
DLL has brought the CLK0 signal in phase with the CLKIN
signal, it asserts the LOCKED output, indicating a “lock” on
to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the
DLL component through the use of the attributes described
in Table 13. Each attribute is described in detail in the sec-
tions that follow:
DS099-2 (v1.2) July 11, 2003
www.xilinx.com
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Advance Product Specification
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