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XC3S50 Datasheet, PDF (21/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology
Spartan-3 1.2V FPGA Family: Functional Description
R
WEA
ENA
SSRA
CLKA
ADDRA[rA 1:0]
DIA[wA 1:0]
DIPA[3:0]
RAM16_wA_wB
DOPA[pA 1:0]
DOA[wA 1:0]
WEB
ENB
SSRB
CLKB
ADDRB[rB 1:0]
DIB[wB 1:0]
DIPB[3:0]
DOPB[pB 1:0]
DOB[wB 1:0]
WE
EN
SSR
CLK
ADDR[r 1:0]
DI[w 1:0]
DIP[p 1:0]
RAM16_Sw
DOP[p 1:0]
DO[w 1:0]
(a) Dual-Port
(b) Single-Port
DS099-2_13_091302
Notes:
1. wA and wB are integers representing the total data path width (i.e., data bits plus parity bits) at ports A and B, respectively.
2. pA and pB are integers that indicate the number of data path lines serving as parity bits.
3. rA and rB are integers representing the address bus width at ports A and B, respectively.
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 8: Block RAM Primitives
Table 9: Block RAM Port Signals
Signal
Description
Port A
Signal
Name
Port B
Signal
Name
Address Bus
ADDRA
ADDRB
Data Input Bus
DIA
DIB
Parity Data
Input(s)
DIPA
DIPB
Direction
Function
Input
The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path
determines the number of available address lines (r).
Input
Data at the DI input bus is written to the addressed memory
location addressed on an enabled active CLK edge.
It is possible to configure a port’s total data path width (w) to be
1, 2, 4, 9, 18, or 36 bits. This selection applies to both the DI and
DO paths of a given port. Each port is independent. For a port
assigned a width (w), the number of addressable locations will
be 16,384/(w-p) where "p" is the number of parity bits. Each
memory location will have a width of "w" (including parity bits).
See the DIP signal description for more information of parity.
Input
Parity inputs represent additional bits included in the data input
path to support error detection. The number of parity bits "p"
included in the DI (same as for the DO bus) depends on a port’s
total data path width (w). See Table 10.
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DS099-2 (v1.2) July 11, 2003
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