XC3S50 Datasheet, PDF (102/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Spartan-3 FPGA Family: Pinout Descriptions
If designing for footprint compatibility across the range of
devices in a specific package, and if the VREF_# pins within
a bank connect to an input reference voltage, then also con-
nect any N.C. (not connected) pins on the smaller devices in
that package to the input reference voltage. More details are
provided later for each package type.
N.C. Type: Unconnected Package Pins
Pins marked as “N.C.” are unconnected for the specific
device/package combination. For other devices in this same
package, this pin may be used as an I/O or VREF connec-
tion. In both the pinout tables and the footprint diagrams,
unconnected pins are noted with either a black diamond
symbol (‹) or a black square symbol („).
If designing for footprint compatibility across multiple device
densities, check the pin types of the other Spartan-3
devices available in the same footprint. If the N.C. pin
matches to VREF pins in other devices, and the VREF pins
are used in the associated I/O bank, then connect the N.C.
to the VREF voltage source.
VCCO Type: Output Voltage Supply for I/O
Bank
Each I/O bank has its own set of voltage supply pins that
determines the output voltage for the output buffers in the
I/O bank. Furthermore, for some I/O standards such as
LVCMOS, LVCMOS25, LVTTL, etc., VCCO sets the input
threshold voltage on the associated input buffers.
Spartan-3 devices are designed and characterized to sup-
port various I/O standards for VCCO values of +1.2V, +1.5V,
+1.8V, +2.5V, and +3.3V.
Most VCCO pins are labeled as VCCO_# where the ‘#’
symbol represents the associated I/O bank number, an inte-
ger ranging from 0 to 7. In the 144-pin TQFP package
(TQ144) however, the VCCO pins along an edge of the
device are combined into a single VCCO input. For exam-
ple, the VCCO inputs for Bank 0 and Bank 1 along the top
edge of the package are combined and relabeled
VCCO_TOP. The bottom, left, and right edges are similarly
combined.
In Serial configuration mode, VCCO_4 must be at a level
compatible with the attached configuration memory or data
source. In Parallel configuration mode, both VCCO_4 and
VCCO_5 must be at the same compatible voltage level.
All VCCO inputs to a bank must be connected together and
to the voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as
described in XAPP623: Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors.
VCCINT Type: Voltage Supply for Internal
Core Logic
Internal core logic circuits such as the configurable logic
blocks (CLBs) and programmable interconnect operate
from the VCCINT voltage supply inputs. VCCINT must be
+1.2V.
All VCCINT inputs must be connected together and to the
+1.2V voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as
described in XAPP623: Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors.
VCCAUX Type: Voltage Supply for Auxiliary
Logic
The VCCAUX pins supply power to various auxiliary cir-
cuits, such as to the Digital Clock Managers (DCMs), the
JTAG pins, and to the dedicated configuration pins (CON-
FIG type). VCCAUX must be +2.5V.
All VCCAUX inputs must be connected together and to the
+2.5V voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as
described in XAPP623: Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors.
Because VCCAUX connects to the DCMs and the DCMs
are sensitive to voltage changes, be sure that the VCCAUX
supply and the ground return paths are designed for low
noise and low voltage drop, especially that caused by a
large number of simultaneous switching I/Os.
GND Type: Ground
All GND pins must be connected and have a low resistance
path back to the various VCCO, VCCINT, and VCCAUX
supplies.
Pin Behavior During Configuration
Table 10 shows how various pins behave during the FPGA
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP_EN pin. The mode select pins determine which
of the DUAL type pins are active during configuration. In
JTAG configuration mode, none of the DUAL-type pins are
used for configuration and all behave as user-I/O pins.
All DUAL-type pins not actively used during configuration
and all I/O-type, DCI-type, VREF-type, GCLK-type pins are
high impedance (floating, three-stated, Hi-Z) during the
configuration process. These pins are indicated in Table 10
as shaded table entries or cells. These pins have a weak
pull-up resistor to their associated VCCO if the HSWAP_EN
pin is Low.
After configuration completes, some pins have optional
behavior controlled by the configuration bitstream loaded
into the part. For example, via the bitstream, all unused I/O
pins can collectively be configured to have a weak pull-up
resistor, a weak pull-down resistor, or be left in a
high-impedance state.
DS099-4 (v1.5) July 13, 2004
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