XC3S50 Datasheet, PDF (24/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 1.2V FPGA Family: Functional Description
CLK
WE
DI
ADDR
DO
0000
XXXX
1111
2222
aa
bb
cc
MEM(aa)
1111
2222
XXXX
dd
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS099-2_14_030403
Figure 9: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Choosing the READ_FIRST attribute, data already stored in
the addressed location pass to the DO outputs before that
location is over-written with new data from the DI inputs on
an enabled active CLK edge. READ_FIRST timing is shown
in the portion of Figure 10 during which WE is High.
CLK
WE
DI
ADDR
DO
0000
XXXX
1111
2222
XXXX
aa
bb
cc
dd
MEM(aa)
old MEM(bb)
old MEM(cc)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS099-2_15_030403
Figure 10: Waveforms of Block RAM Data Operations with READ_FIRST Selected
Choosing a third attribute called NO_CHANGE puts the DO
outputs in a latched state when asserting WE. Under this
condition, the DO outputs will retain the data driven just
before WE was asserted. NO_CHANGE timing is shown in
the portion of Figure 11 during which WE is High.
DS099-2 (v1.2) July 11, 2003
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Advance Product Specification
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