XC3S50 Datasheet, PDF (74/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 26: Block RAM Timing
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Clock-to-Output Times
T_BCKO
When reading from the Block
-
2.10
-
2.41
RAM, the time from the active
transition at the CLK input to
data appearing at the DOUT
output
Setup Times
T_BDCK
Time from the setup of data at
0.43
-
0.49
-
the DIN inputs to the active
transition at the CLK input of the
Block RAM
Hold Times
T_BCKD
Time from the active transition
0
-
0
-
at the Block RAM’s CLK input to
the point where data is last held
at the DIN inputs
Clock Timing
T_BPWH
The High pulse width of the
1.26
-
1.44
-
Block RAM’s CLK signal
T_BPWL
The Low pulse width of the CLK
1.26
-
1.44
-
signal
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5.
Units
ns
ns
ns
ns
ns
DS099-3 (v1.3) March 4, 2004
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