XC3S50 Datasheet, PDF (47/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 1.2V FPGA Family: Functional Description
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Revision History
Date
04/11/03
05/19/03
07/11/03
Version No.
1.0
1.1
1.2
Description
Initial Xilinx release
Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions.
Explained the configuration port Persist option in Slave Parallel Mode section. Updated
Figure 2 and Double-Data-Rate Transmission section to indicate that DDR clocking for the
XCS350 is the same as that for all other Spartan-3 devices. Updated description of I/O voltage
tolerance in ESD Protection section. In Table 6, changed input termination type for DCI
version of the LVCMOS standard to None. Added additional flexibility for making DLL
connections in Figure 15 and accompanying text. In the Configuration section, inserted an
explanation of how to choose power supplies for the configuration interface, including
guidelines for achieving 3.3V-tolerance.
The Spartan-3 Family Data Sheet
DS099-1, Spartan-3 1.2V FPGA Family: Introduction and Ordering Information (Module 1)
DS099-2, Spartan-3 1.2V FPGA Family: Functional Description (Module 2)
DS099-3, Spartan-3 1.2V FPGA Family: DC and Switching Characteristics (Module 3)
DS099-4, Spartan-3 1.2V FPGA Family: Pinout Descriptions (Module 4)
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www.xilinx.com
DS099-2 (v1.2) July 11, 2003
1-800-255-7778
Advance Product Specification
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