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R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 14: Setup and Hold Times for the IOB Input Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Min
Min
Units
Setup Times
T_IOPICK
T_IOPICKD
Time from the setup of data
at the Input pin to the active
transition at the ICLK input
of the Input Flip-Flop (IFF).
No input delay is
programmed.
Time from the setup of data
at the Input pin to the active
transition at the IFF’s ICLK
input. The input delay is
programmed.
LVCMOS25⁽²⁾,
IOBDELAY = NONE
LVCMOS25⁽²⁾,
IOBDELAY = IFD
All
XC3S50
XC3S200
XC3S400
XC3S1000
1.15
1.32
ns
3.26
3.75
ns
3.89
4.47
ns
3.89
4.47
ns
4.15
4.77
ns
XC3S1500
4.32
4.97
ns
XC3S2000
4.50
5.17
ns
XC3S4000
4.67
5.37
ns
XC3S5000
5.02
5.77
ns
Hold Times
T_IOICKP
T_IOICKPD
Time from the active
transition at the IFF’s ICLK
input to the point where
data must be held at the
Input pin. No input delay is
programmed.
Time from the active
transition at the IFF’s ICLK
input to the point where
data must be held at the
Input pin. The input delay is
programmed.
LVCMOS25⁽³⁾,
IOBDELAY = NONE
LVCMOS25⁽³⁾,
IOBDELAY = IFD
All
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
–0.66
ns
–2.36
ns
–2.87
ns
–2.87
ns
–3.08
ns
–3.22
ns
XC3S2000
–3.36
ns
XC3S4000
–3.50
ns
XC3S5000
–3.78
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set
forth in Table 5 and Table 8.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true,
add the appropriate Input adjustment from Table 16.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true,
subtract the appropriate Input adjustment from Table 16. When the hold time is negative, it is possible to change the data before the
clock’s active edge.
DS099-3 (v1.3) March 4, 2004
www.xilinx.com
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