XC3S50 Datasheet, PDF (133/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: Pinout Descriptions
Table 25: FG320 Package Pinout (Continued)
Bank
XC3S400
XC3S1000
XC3S1500
Pin Name
FG320
Pin
Number
Type
7
IO_L27N_7
H5
I/O
7
IO_L27P_7/VREF_7
H6
VREF
7
IO_L34N_7
H4
I/O
7
IO_L34P_7
H3
I/O
7
IO_L35N_7
H1
I/O
7
IO_L35P_7
H2
I/O
7
IO_L39N_7
J1
I/O
7
IO_L39P_7
J2
I/O
7
IO_L40N_7/VREF_7
J5
VREF
7
IO_L40P_7
J4
I/O
7
VCCO_7
F3
VCCO
7
VCCO_7
H7
VCCO
7
VCCO_7
J7
VCCO
N/A GND
A1
GND
N/A GND
A13
GND
N/A GND
A18
GND
N/A GND
A6
GND
N/A GND
B17
GND
N/A GND
B2
GND
N/A GND
C10
GND
N/A GND
C9
GND
N/A GND
F1
GND
N/A GND
F18
GND
N/A GND
G12
GND
N/A GND
G7
GND
N/A GND
H10
GND
N/A GND
H11
GND
N/A GND
H8
GND
N/A GND
H9
GND
N/A GND
J11
GND
N/A GND
J16
GND
N/A GND
J3
GND
N/A GND
J8
GND
N/A GND
K11
GND
N/A GND
K16
GND
N/A GND
K3
GND
N/A GND
K8
GND
N/A GND
L10
GND
N/A GND
L11
GND
N/A GND
L8
GND
N/A GND
L9
GND
N/A GND
M12
GND
R
Table 25: FG320 Package Pinout (Continued)
Bank
XC3S400
XC3S1000
XC3S1500
Pin Name
FG320
Pin
Number
Type
N/A GND
M7
GND
N/A GND
N1
GND
N/A GND
N18
GND
N/A GND
T10
GND
N/A GND
T9
GND
N/A GND
U17
GND
N/A GND
U2
GND
N/A GND
V1
GND
N/A GND
V13
GND
N/A GND
V18
GND
N/A GND
V6
GND
N/A VCCAUX
B12
VCCAUX
N/A VCCAUX
B7
VCCAUX
N/A VCCAUX
G17
VCCAUX
N/A VCCAUX
G2
VCCAUX
N/A VCCAUX
M17
VCCAUX
N/A VCCAUX
M2
VCCAUX
N/A VCCAUX
U12
VCCAUX
N/A VCCAUX
U7
VCCAUX
N/A VCCINT
F12
VCCINT
N/A VCCINT
F13
VCCINT
N/A VCCINT
F6
VCCINT
N/A VCCINT
F7
VCCINT
N/A VCCINT
G13
VCCINT
N/A VCCINT
G6
VCCINT
N/A VCCINT
M13
VCCINT
N/A VCCINT
M6
VCCINT
N/A VCCINT
N12
VCCINT
N/A VCCINT
N13
VCCINT
N/A VCCINT
N6
VCCINT
N/A VCCINT
N7
VCCINT
VCCAUX CCLK
T15
CONFIG
VCCAUX DONE
R15
CONFIG
VCCAUX HSWAP_EN
E6
CONFIG
VCCAUX M0
P5
CONFIG
VCCAUX M1
U3
CONFIG
VCCAUX M2
R4
CONFIG
VCCAUX PROG_B
E5
CONFIG
VCCAUX TCK
E14
JTAG
VCCAUX TDI
D4
JTAG
VCCAUX TDO
D15
JTAG
VCCAUX TMS
B16
JTAG
46
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