XC3S50 Datasheet, PDF(69/192 Page) Xilinx, Inc – Revolutionary 90-nanometer process technology

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XC3S50 Datasheet, PDF (69/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Spartan-3 FPGA Family: DC and Switching Characteristics

The capacitive load (CL) is connected between the output

and GND. The Output timing for all standards, as published

in the speed files and the data sheet, is always based on a

CL value of zero unless otherwise specified. High-imped-

ance probes (less than 1 pF) are used for all measure-

ments. Any delay that the test fixture might contribute to test

measurements is subtracted from those measurements to

produce the final timing numbers as published in the speed

files and data sheet.

Using IBIS Models to Simulate Load

Conditions in Application

IBIS Models permit the most accurate prediction of timing

delays for a given application. The parameters found in the

IBIS model (VREF, RREF, CREF, and VMEAS) correspond

directly with the parameters used in Table 20, VT, RT, CL,

and VM. Do not confuse VREF (the termination voltage) from

the IBIS model with VREF (the input-switching threshold)

from the table! The four parameters describe all relevant

output test conditions.

Simultaneously Switching Output Guidelines

IBIS models are found at the following link:

http://www.xilinx.com/support/sw_ibis.htm

Simulate delays for a given application according to its spe-

cific load conditions as follows:

1. Simulate the desired signal standard with the output

driver connected to the test setup shown in Figure 4.

Use parameter values VT, RT, CL, and VM from

Table 20.

2. Record the time to VM.

3. Simulate the same signal standard with the output

driver connected to the PCB trace with load. Use the

appropriate IBIS model (including VREF, RREF, CREF,

and VMEAS values) or capacitive value to represent the

load.

4. Record the time to VMEAS.

5. Compare the results of steps 2 and 4. The increase (or

decrease) in delay should be added to (or subtracted

from) the appropriate Output standard adjustment

(Table 19) to yield the worst-case delay of the PCB

trace.

Table 21: Equivalent VCCO/GND Pairs per Bank

Device VQ100 TQ144 PQ208 FT256

XC3S50

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

FG320

FG456

FG676

FG900

FG1156

www.xilinx.com

DS099-3 (v1.3) March 4, 2004

1-800-255-7778

Advance Product Specification

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