XC3S50 Datasheet, PDF (45/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 1.2V FPGA Family: Functional Description
R
Power-On
Set PROG_B Low
after Power-On
V_CCINT >1V
and V_CCAUX > 2V
No
and V_CCO Bank 4 > 1V
Yes
Clear
configuration
memory
No
INIT_B = High?
Yes
PROG_B = Low
No
Yes
Sample
mode pins
(JTAG port becomes
available)
Load CFG_IN
instruction
Load configuration
data frames
Shutdown
sequence
Load
JShutdown
instruction
CRC
correct?
No _{INIT_B goes Low.}
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
No
Yes
Reconfigure?
DS099_27_041103
Figure 24: Boundary-Scan Configuration Flow Diagram
38
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DS099-2 (v1.2) July 11, 2003
1-800-255-7778
Advance Product Specification
40