XC3S50 Datasheet, PDF (112/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: Pinout Descriptions
Table 16: VQ100 Package Pinout
Bank
XC3S50
XC3S200
Pin Name
7
VCCO_7
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A GND
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCAUX
N/A VCCINT
N/A VCCINT
N/A VCCINT
VQ100 Pin
Number Type
P6
VCCO
P3
GND
P10
GND
P20
GND
P29
GND
P41
GND
P56
GND
P66
GND
P73
GND
P82
GND
P95
GND
P7
VCCAUX
P33 VCCAUX
P58 VCCAUX
P84 VCCAUX
P18
VCCINT
P45
VCCINT
P69
VCCINT
Table 16: VQ100 Package Pinout
Bank
XC3S50
XC3S200
Pin Name
N/A VCCINT
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
VCCAUX M1
VCCAUX M2
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
VQ100 Pin
Number Type
P93
VCCINT
P52 CONFIG
P51 CONFIG
P98 CONFIG
P25 CONFIG
P24 CONFIG
P26 CONFIG
P99 CONFIG
P77
JTAG
P100
JTAG
P76
JTAG
P78
JTAG
User I/Os by Bank
Table 17 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks on the VQ100 pack-
age.
Table 17: User I/Os Per Bank in VQ100 Package
Maximum
Package Edge I/O Bank
I/O
I/O
0
6
1
Top
1
7
2
2
8
5
Right
3
8
5
4
10
0
Bottom
5
8
0
6
8
4
Left
7
8
5
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
1
0
2
1
0
2
1
0
2
1
6
2
0
6
0
0
0
2
2
0
2
1
GCLK
2
2
0
0
2
2
0
0
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
25
Product Specification
1-800-255-7778