XC3S50 Datasheet, PDF (25/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 1.2V FPGA Family: Functional Description
R
CLK
WE
DI
XXXX
1111
2222
XXXX
ADDR
aa
bb
cc
dd
DO
0000
MEM(aa)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
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Figure 11: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Dedicated Multipliers
All Spartan-3 devices provide embedded multipliers that
accept two 18-bit words as inputs to produce a 36-bit prod-
uct. This section provides an introduction to multipliers. For
further details, see XAPP467: Using Embedded Multipliers
in Spartan-3 FPGAs.
The input buses to the multiplier accept data in two’s-com-
plement form (either 18-bit signed or 17-bit unsigned). One
such multiplier is matched to each block RAM on the die.
The close physical proximity of the two ensures efficient
data handling. Cascading multipliers permits multiplicands
more than three in number as well as wider than 18-bits.
The multiplier is placed in a design using one of two primi-
tives: an asynchronous version called MULT18X18 and a
version with a register at the outputs called MULT18X18S,
as shown in Figure 12a and Figure 12b, respectively. The
signals for these primitives are defined in Table 11.
The CORE Generator system produces multipliers based
on these primitives that can be configured to suit a wide
range of requirements.
A[17:0]
B[17:0]
MULT18X18
P[35:0]
(a) Asynchronous 18-bit Multiplier
A[17:0]
B[17:0]
CLK
CE
RST
MULT18X18S
P[35:0]
(b) 18-bit Multiplier with Register at Outputs
Figure 12: Embedded Multiplier Primitives
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