XC3S50 Datasheet, PDF (31/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 1.2V FPGA Family: Functional Description
R
Their relative timing in the Low Frequency Mode is shown in
Figure 16. The CLK90, CLK180 and CLK270 outputs are
not available when operating in the High Frequency mode.
(See the description of the DLL_FREQUENCY_MODE
attribute in Table 13.) For control in finer increments than
90°, see the Phase Shifter (PS), page 26 section.
Basic Frequency Synthesis Outputs of the DLL
Component
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also dou-
bles the frequency, but is 180° out-of-phase with respect to
CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to var-
ious values as described in Table 13. The basic frequency
synthesis outputs are described in Table 12. Their relative
timing in the Low Frequency Mode is shown in Figure 16.
The CLK2X and CLK2X180 outputs are not available when
operating in the High Frequency mode. (See the description
of the DLL_FREQUENCY_MODE attribute in Table 14.)
Duty Cycle Correction of DLL Clock Outputs
The CLK2X⁽¹⁾, CLK2X180, and CLKDV⁽²⁾ output signals
ordinarily exhibit a 50% duty cycle – even if the incoming
CLKIN signal has a different duty cycle. Fifty-percent duty
cycle means that the High and Low times of each clock
cycle are equal. The DUTY_CYCLE_CORRECTION
attribute determines whether or not duty cycle correction is
applied to the CLK0, CLK90, CLK180 and CLK270 outputs.
If DUTY_CYCLE_CORRECTION is set to TRUE, then the
duty cycle of these four outputs is corrected to 50%. If
DUTY_CYCLE_CORRECTION is set to FALSE, then these
outputs exhibit the same duty cycle as the CLKIN signal.
Figure 16 compares the characteristics of the DLL’s output
signals to those of the CLKIN signal.
Phase:
0^o 90^o 180^o 270^o 0^o 90^o 180^o 270^o 0^o
Input Signal (30% Duty Cycle)
t
CLKIN
Output Signal - Duty Cycle is Always Corrected
CLK2X
CLK2X180
CLKDV(1)
Output Signal - Attribute Corrects Duty Cycle
DUTY_CYCLE_CORRECTION = FALSE
CLK0
CLK90
CLK180
CLK270
DUTY_CYCLE_CORRECTION = TRUE
CLK0
CLK90
CLK180
CLK270
Notes:
1. The DLL attribute CLKDV_DIVIDE is set to 2.
DS099-2_10_031303
Figure 16: Characteristics of the DLL Clock Outputs
1. The CLK2X output generates a 25% duty cycle clock at the same frequency as the CLKIN signal until the DLL has achieved lock.
2. The duty cycle of the CLKDV outputs may differ somewhat from 50% (i.e., the signal will be High for less than 50% of the period) when
the CLKDV_DIVIDE attribute is set to a non-integer value and the DLL is operating in the High Frequency mode.
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DS099-2 (v1.2) July 11, 2003
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Advance Product Specification
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