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Spartan-3 FPGA Family: DC and Switching Characteristics
Revision History
Date
04/11/03
07/11/03
02/06/04
03/04/04
Version No.
Description
1.0
Initial Xilinx release.
1.1
Extended Absolute Maximum Rating for junction temperature in Table 1. Added numbers for
typical quiescent supply current (Table 7) and DLL timing.
1.2
Revised V_IN maximum rating (Table 1). Added power-on requirements (Table 3), leakage
current number (Table 6), and differential output voltage levels (Table 11) for Rev. 0. Published
new quiescent current numbers (Table 7). Updated pull-up and pull-down resistor strengths
(Table 6). Added LVDCI_DV2 and LVPECL standards (Table 10 and Table 11). Changed
CCLK setup time (Table 35 and Table 36).
1.3
Added timing numbers from v1.29 speed files as well as DCM timing (Table 27 through
Table 32).
The Spartan-3 Family Data Sheet
DS099-1, Spartan-3 FPGA Family: Introduction and Ordering Information (Module 1)
DS099-2, Spartan-3 FPGA Family: Functional Description (Module 2)
DS099-3, Spartan-3 FPGA Family: DC and Switching Characteristics (Module 3)
DS099-4, Spartan-3 FPGA Family: Pinout Descriptions (Module 4)
DS099-3 (v1.3) March 4, 2004
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Advance Product Specification
1-800-255-7778
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