XC3S50 Datasheet, PDF (82/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: DC and Switching Characteristics
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Input/Output)
DIN
(Input)
DOUT
(Output)
T_DCC
T_CCD
Bit 0
Bit 1
T_CCH
T_CCL
1/F_CCSER
Bit n Bit n+1
T_CCO
Bit n-64 Bit n-63
DS099-3_04_041103
Notes:
1. The CS_B, WRITE_B, and BUSY signals are not used in the serial modes. Keep the CS_B and WRITE_B inputs inactive (i.e., both
pins High).
Figure 6: Waveforms for Master and Slave Serial Configuration
Table 35: Timing for the Master and Slave Serial Configuration Modes
Symbol
Description
Slave/Master
Clock-to-Output Times
T_CCO
The time from the rising transition on the
CCLK pin to data appearing at the DOUT pin
Both
Setup Times
T_DCC
The time from the setup of data at the DIN pin
to the rising transition at the CCLK pin
Both
Hold Times
T_CCD
The time from the rising transition at the
CCLK pin to the point when data is last held
at the DIN pin
Both
Clock Timing
T_CCH
T_CCL
F_CCSER
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal at the CCLK
input pin
Slave
∆F_CCSER
Variation from the generated CCLK frequency
set using the ConfigRate BitGen option
Master
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5.
All Speed Grades
Min
Max
-
12.0
-
10.0
-
0
5.0
5.0
-
–50%
-
-
66
+50%
Units
ns
ns
ns
ns
ns
MHz
-
DS099-3 (v1.3) March 4, 2004
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35
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