XC3S50 Datasheet, PDF (123/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: Pinout Descriptions
PQ208 Footprint
Left Half of Package
(top view)
XC3S50
(124 max. user I/O)
72
I/O: Unrestricted,
general-purpose user I/O
16
VREF: User I/O or input
voltage reference for bank
17
N.C.: Unconnected pins for
XC3S50 (‹)
XC3S200, XC3S400
(141 max user I/O)
83
I/O: Unrestricted,
general-purpose user I/O
22
VREF: User I/O or input
voltage reference for bank
0
N.C.: No unconnected pins
in this package
All devices
12
DUAL: Configuration pin,
then possible user I/O
8
GCLK: User I/O or global
clock buffer input
16
DCI: User I/O or reference
resistor input for bank
7
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG
port pins
4
VCCINT: Internal core
voltage supply (+1.2V)
12
VCCO: Output voltage
supply for bank
8
VCCAUX: Auxiliary voltage
supply (+2.5V)
28 ^{GND: Ground}
GND 1
IO_L01P_7/VRN_7 2
IO_L01N_7/VRP_7 3
(‹) IO_L16P_7/VREF_7 4
(‹) IO_L16N_7 5
VCCO_7 6
IO_L19P_7 7
GND 8
IO_L19N_7/VREF_7 9
IO_L20P_7 10
IO_L20N_7 11
IO_L21P_7 12
IO_L21N_7 13
GND 14
IO_L22P_7 15
IO_L22N_7 16
VCCAUX 17
IO_L23P_7 18
IO_L23N_7 19
IO_L24P_7 20
IO_L24N_7 21
(‹) IO_L39P_7 22
VCCO_7 23
(‹) IO_L39N_7 24
GND 25
IO_L40P_7 26
IO_L40N_7/VREF_7 27
IO_L40P_6/VREF_6 28
IO_L40N_6 29
GND 30
(‹) IO_L39P_6 31
VCCO_6 32
(‹) IO_L39N_6 33
IO_L24P_6 34
IO_L24N_6/VREF_6 35
IO_L23P_6 36
IO_L23N_6 37
VCCAUX 38
IO_L22P_6 39
IO_L22N_6 40
GND 41
IO_L21P_6 42
IO_L21N_6 43
IO_L20P_6 44
IO_L20N_6 45
IO_L19P_6 46
GND 47
IO_L19N_6 48
VCCO_6 49
(‹) IO/VREF_6 50
IO_L01P_6/VRN_6 51
IO_L01N_6/VRP_6 52
R
Bank 0
Bank 5
DS099-4_09a_121103
Figure 10: PQ208 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.
36
www.xilinx.com
DS099-4 (v1.5) July 13, 2004
1-800-255-7778
Product Specification