XC3S50 Datasheet, PDF (55/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: DC and Switching Characteristics
R
Internal
Logic
V_INP
P ^Differential
N ^{I/O Pair Pins}
V_INN
V_INN
V_INP
50%
V_ID
V_ICM
GND level
V_ICM
=
Input
common
mode
voltage
=
V_INP
+
2
V_INN
V_ID = Differential input voltage = V_INP - V_INN
DS099-3_01_012304
Figure 1: Differential Input Voltages
Table 10: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
V_CCO(1)
V_ID
V_ICM
V_IH
Min Nom Max Min Nom Max Min Nom Max Min Max
Signal Standard (V) (V) (V) (mV) (mV) (mV) (V) (V) (V) (V) (V)
LDT_25
2.375 2.50 2.625 200 600 1000 0.44 0.60 0.78
-
-
LVDS_25,
2.375 2.50 2.625 100 350 600 0.30 1.25 2.20
-
-
LVDS_25_DCI
BLVDS_25
2.375 2.50 2.625 -
350
-
-
1.25
-
-
-
LVDSEXT_25,
2.375 2.50 2.625 100 540 1000 0.30 1.20 2.20
-
-
LVDSEXT_25_DCI
ULVDS_25
2.375 2.50 2.625 200 600 1000 0.44 0.60 0.78
-
-
LVPECL_25
2.375 2.50 2.625 100
-
-
-
-
-
0.8 2.0
RSDS_25
2.375 2.50 2.625 100 200
-
-
1.20
-
-
-
Notes:
1. V_CCO only supplies differential output drivers, not input circuits.
2. V_REF inputs are not used for any of the differential I/O standards.
3. V_ID is a differential measurement.
V_IL
Min Max
(V) (V)
-
-
-
-
-
-
-
-
-
-
0.5 1.7
-
-
8
www.xilinx.com
DS099-3 (v1.3) March 4, 2004
1-800-255-7778
Advance Product Specification