XC3S50 Datasheet, PDF (168/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 35 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks for the XC3S2000 in
the FG900 package. Similarly, Table 36 shows how the
available user-I/O pins are distributed between the eight I/O
banks for the XC3S4000 and XC3S5000 in the FG900
package.
Table 35: User I/Os Per Bank for XC3S2000 in FG900 Package
Edge
I/O
Maximum
Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
71
62
0
2
5
Top
1
71
62
0
2
5
2
69
61
0
2
6
Right
3
71
62
0
2
7
4
72
57
6
2
5
Bottom
5
71
55
6
2
6
6
69
60
0
2
7
Left
7
71
62
0
2
7
GCLK
2
2
0
0
2
2
0
0
Table 36: User I/Os Per Bank for XC3S4000 and XC3S5000 in FG900 Package
Edge
I/O
Maximum
Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
79
70
0
2
5
Top
1
79
70
0
2
5
2
79
71
0
2
6
Right
3
79
70
0
2
7
4
80
65
6
2
5
Bottom
5
79
63
6
2
6
6
79
70
0
2
7
Left
7
79
70
0
2
7
GCLK
2
2
0
0
2
2
0
0
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
81
Product Specification
1-800-255-7778