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R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 36: Timing for the Master and Slave Parallel Configuration Modes (Continued)
All Speed Grades
Symbol
Description
Slave/Master Min
Max Units
Hold Times
T_SMCCD
The time from the rising transition at the CCLK pin to the
point when data is last held at the D0-D7 pins
Both
0
-
ns
T_SMCCCS
T_SMWCC(2)
The time from the rising transition at the CCLK pin to the
point when a logic level is last held at the CS_B pin
The time from the rising transition at the CCLK pin to the
point when a logic level is last held at the RDWR_B pin
0
-
ns
0
-
ns
Clock Timing
T_CCH
T_CCL
F_CCPAR
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal Not using the BUSY pin⁽³⁾
at the CCLK input pin
Using the BUSY pin
Slave
5
-
ns
5
-
ns
-
66
MHz
-
100 MHz
∆F_CCPAR
Variation from the generated CCLK frequency set using
the BitGen option ConfigRate
Master
–50% +50%
-
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5.
2. RDWR_B is synchronized to CCLK for the purpose of performing the Abort operation. The same pin asynchronously controls the
driver impedance of the D0 - D7 pins. To avoid contention when writing configuration data to the D0 - D7 bus, do not bring RDWR_B
High when CS_B is Low.
3. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
DS099-3 (v1.3) March 4, 2004
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