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XC3S50 Datasheet, PDF (4/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology
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Spartan-3 FPGA Family: Introduction and Ordering Information
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust static memory cells that collectively control
all functional elements and routing resources. Before pow-
ering on the FPGA, configuration data is stored externally in
a PROM or some other nonvolatile medium either on or off
the board. After applying power, the configuration data is
written to the FPGA using any of five different modes: Mas-
ter Parallel, Slave Parallel, Master Serial, Slave Serial and
Boundary Scan (JTAG). The Master and Slave Parallel
modes use an 8-bit wide SelectMAP™ port.
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 17 sin-
gle-ended standards and seven differential standards as
listed in Table 2. Many standards support the DCI feature,
which uses integrated terminations to eliminate unwanted
signal reflections. Table 3 shows the number of user I/Os as
well as the number of differential I/O pairs available for each
device/package combination.
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Category
Description
VCCO
(V)
Class
Symbol
DCI
Option
Single-Ended
GTL
Gunning Transceiver Logic
N/A
Terminated
GTL
Yes
Plus
GTLP
Yes
HSTL
High-Speed Transceiver Logic
1.5
I
HSTL_I
Yes
III
HSTL_III
Yes
1.8
I
HSTL_I_18
Yes
II
HSTL_II_18
Yes
III
HSTL_III_18
Yes
LVCMOS Low-Voltage CMOS
1.2
N/A
LVCMOS12
No
1.5
N/A
LVCMOS15
Yes
1.8
N/A
LVCMOS18
Yes
2.5
N/A
LVCMOS25
Yes
3.3
N/A
LVCMOS33
Yes
LVTTL
Low-Voltage Transistor-Transistor Logic
3.3
N/A
LVTTL
No
PCI
Peripheral Component Interconnect
3.0
33 MHz
PCI33_3
No
SSTL
Stub Series Terminated Logic
1.8
N/A
SSTL18_I
Yes
2.5
I
SSTL2_I
Yes
II
SSTL2_II
Yes
Differential
LDT
Lightning Data Transport
(HyperTransport™)
2.5
N/A
LDT_25
No
LVDS
Low-Voltage Differential Signaling
Standard
LVDS_25
Yes
Bus
BLVDS_25
No
Extended Mode
LVDSEXT_25 Yes
Ultra
ULVDS_25
No
LVPECL
Low-Voltage Positive Emitter-Coupled
2.5
N/A
Logic
LVPECL_25
No
RSDS
Reduced-Swing Differential Signaling
2.5
N/A
RSDS_25
No
DS099-1 (v1.2) December 24, 2003
www.xilinx.com
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