XC3S50 Datasheet, PDF (104/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: Pinout Descriptions
Table 10: Pin Behavior After Power-Up, During Configuration (Continued)
Configuration Mode Settings <M2:M1:M0>
Serial Modes
SelectMap Parallel Modes
Pin Name
Master
<0:0:0>
Slave
<1:1:1>
Master
<0:1:1>
Slave
<1:1:0>
GCLK: Global clock buffer inputs
IO_Lxxy_#/
GCLK0 through
GCLK7
VREF: I/O bank input reference voltage pins
IO_Lxxy_#/
VREF_#
IO/VREF_#
CONFIG: Dedicated configuration pins
CCLK
CCLK (O)
CCLK (I)
CCLK (O)
CCLK (I)
JTAG Mode
<1:0:1>
PROG_B
DONE
PROG_B (I)
(pull-up)
DONE (I/OD)
PROG_B (I)
(pull-up)
DONE (I/OD)
PROG_B (I)
(pull-up)
DONE (I/OD)
PROG_B (I)
(pull-up)
DONE (I/OD)
PROG_B (I),
Via JPROG_B
instruction
DONE (I/OD)
M2
M2=0 (I)
M2=1 (I)
M1
M1=0 (I)
M1=1 (I)
M0
M0=0 (I)
M0=1 (I)
HSWAP_EN
HSWAP_EN HSWAP_EN
(I)
(I)
JTAG: JTAG interface pins
TDI
TDI (I)
TDI (I)
TMS
TMS (I)
TMS (I)
TCK
TCK (I)
TCK (I)
TDO
TDO (O)
TDO (O)
VCCO: I/O bank output voltage supply pins
VCCO_4
Same voltage
(for DUAL pins) as external
interface
Same voltage
as external
interface
VCCO_5
(for DUAL pins)
VCCO_5
VCCO_5
VCCO_#
VCCO_#
VCCO_#
VCCAUX: Auxiliary voltage supply pins
VCCAUX
+2.5V
+2.5V
M2=0 (I)
M1=1 (I)
M0=1 (I)
HSWAP_EN
(I)
TDI (I)
TMS (I)
TCK (I)
TDO (O)
Same voltage
as external
interface
Same voltage
as external
interface
VCCO_#
+2.5V
M2=1 (I)
M1=1 (I)
M0=0 (I)
HSWAP_EN
(I)
TDI (I)
TMS (I)
TCK (I)
TDO (O)
Same voltage
as external
interface
Same voltage
as external
interface
VCCO_#
+2.5V
M2=1 (I)
M1=0 (I)
M0=1 (I)
HSWAP_EN
(I)
TDI (I)
TMS (I)
TCK (I)
TDO (O)
VCCO_4
VCCO_5
VCCO_#
+2.5V
Bitstream
Configuration
Option
UnusedPin
UnusedPin
UnusedPin
CclkPin
ConfigRate
ProgPin
DriveDone
DonePin
DonePipe
M2Pin
M1Pin
M0Pin
HswapenPin
TdiPin
TmsPin
TckPin
TdoPin
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
17
Product Specification
1-800-255-7778