XC3S50 Datasheet, PDF (128/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: Pinout Descriptions
Table 23: FT256 Package Pinout (Continued)
Bank
XC3S200
XC3S400
XC3S1000
Pin Name
FT256
Pin
Number
Type
N/A GND
T16
GND
N/A VCCAUX
A6 VCCAUX
N/A VCCAUX
A11 VCCAUX
N/A VCCAUX
F1 VCCAUX
N/A VCCAUX
F16 VCCAUX
N/A VCCAUX
L1 VCCAUX
N/A VCCAUX
L16 VCCAUX
N/A VCCAUX
T6 VCCAUX
N/A VCCAUX
T11 VCCAUX
N/A VCCINT
D4
VCCINT
N/A VCCINT
D13 VCCINT
N/A VCCINT
E5
VCCINT
N/A VCCINT
E12 VCCINT
N/A VCCINT
M5 VCCINT
N/A VCCINT
M12 VCCINT
N/A VCCINT
N4
VCCINT
Table 23: FT256 Package Pinout (Continued)
Bank
XC3S200
XC3S400
XC3S1000
Pin Name
FT256
Pin
Number
Type
N/A VCCINT
N13 VCCINT
VCCAUX CCLK
T15 CONFIG
VCCAUX DONE
R14 CONFIG
VCCAUX HSWAP_EN
C4 CONFIG
VCCAUX M0
P3 CONFIG
VCCAUX M1
T2
CONFIG
VCCAUX M2
P4 CONFIG
VCCAUX PROG_B
B3 CONFIG
VCCAUX TCK
C14
JTAG
VCCAUX TDI
A2
JTAG
VCCAUX TDO
A15
JTAG
VCCAUX TMS
C13
JTAG
User I/Os by Bank
Table 24 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks on the FT256 package.
Table 24: User I/Os Per Bank in FT256 Package
Maximum
Package Edge I/O Bank
I/O
I/O
0
20
13
Top
1
20
13
Right
2
23
18
3
23
18
4
21
8
Bottom
5
20
7
6
23
18
Left
7
23
18
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
3
0
2
3
0
2
3
0
2
3
6
2
3
6
2
3
0
2
3
0
2
3
GCLK
2
2
0
0
2
2
0
0
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
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Product Specification
1-800-255-7778