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Spartan-3 FPGA Family: Pinout Descriptions
DCI: User I/O or Digitally Controlled
Impedance Resistor Reference Input
These pins are individual user-I/O pins unless one of the I/O
standards used in the bank requires the Digitally Controlled
Impedance (DCI) feature. If DCI is used, then 1% precision
resistors connected to the VRP_# and VRN_# pins match
the impedance on the input or output buffers of the I/O stan-
dards that use DCI within the bank.
The ‘#’ character in the pin name indicates the associated
I/O bank and is an integer, 0 through 7.
There are two DCI pins per I/O bank, except in the TQ144
package, which does not have any DCI inputs for Bank 5.
VRP and VRN Impedance Resistor Reference
Inputs
The 1% precision impedance-matching resistor attached to
the VRP_# pin controls the pull-up impedance of PMOS
transistor in the input or output buffer. Consequently, the
VRP_# pin must connect to ground. The ‘P’ character in
“VRP” indicates that this pin controls the I/O buffer’s PMOS
transistor impedance. The VRP_# pin is used for both single
and split termination.
The 1% precision impedance-matching resistor attached to
the VRN_# pin controls the pull-down impedance of NMOS
transistor in the input or output buffer. Consequently, the
VRN_# pin must connect to VCCO. The ‘N’ character in
“VRN” indicates that this pin controls the I/O buffer’s NMOS
transistor impedance. The VRN_# pin is only used for split
termination.
Each VRN or VRP reference input requires its own resistor.
A single resistor cannot be shared between VRN or VRP
pins associated with different banks.
During configuration, these pins behave exactly like
user-I/O pins. The associated DCI behavior is not active or
valid until after configuration completes.
See “Digitally Controlled Impedance (DCI)” under Functional
Description (Module 2 of the Spartan-3 data sheet).
DCI Termination Types
If the I/O in an I/O bank do not use the DCI feature, then no
external resistors are required and both the VRP_# and
VRN_# pins are available for user I/O, as shown in
Figure 3a.
If the I/O standards within the associated I/O bank require
single termination—such as GTL_DCI, GTLP_DCI, or
HSTL_III_DCI—then only the VRP_# signal connects to a
1% precision impedance-matching resistor, as shown in
Figure 3b. A resistor is not required for the VRN_# pin.
Finally, if the I/O standards with the associated I/O bank
require split termination—such as HSTL_I_DCI,
SSTL2_I_DCI, SSTL2_II_DCI, or LVDS_25_DCI and
LVDSEXT_25_DCI receivers—then both the VRP_# and
VRN_# pins connect to separate 1% precision imped-
ance-matching resistors, as shown in Figure 3c. Neither pin
is available for user I/O.
GCLK: Global Clock Buffer Inputs or
General-Purpose I/O Pins
These pins are user-I/O pins unless they specifically con-
nect to one of the eight low-skew global clock buffers on the
device, specified using the IBUFG primitive.
There are eight GCLK pins per device and two each appear
in the top-edge banks, Bank 0 and 1, and the bottom-edge
banks, Banks 4 and 5. See Figure 1 for a picture of bank
labeling.
During configuration, these pins behave exactly like
user-I/O pins.
CONFIG: Dedicated Configuration Pins
The dedicated configuration pins control the configuration
process and are not available as user-I/O pins. Every pack-
age has seven dedicated configuration pins. All CON-
FIG-type pins are powered by the +2.5V VCCAUX supply.
See “Configuration” under Functional Description (Module 2
of the Spartan-3 data sheet).
CCLK: Configuration Clock
The configuration clock signal on this pin synchronizes the
reading or writing of configuration data. This pin is an input
for the Slave configuration modes, both parallel and serial.
After configuration, the CCLK pin is in a high-impedance,
floating state. By default, CCLK optionally is pulled High to
VCCAUX as defined by the CclkPin bitstream selection. Any
clocks applied to CCLK after configuration are ignored
unless the bitstream option Persist is set to Yes, which
retains the configuration interface. Persist is set to No by
default. However, if Persist is set to Yes, then all clock edges
are potentially active events, depending on the other config-
uration control signals.
The bitstream generator option ConfigRate determines the
frequency of the internally-generated CCLK oscillator
required for the Master configuration modes. The actual fre-
quency is approximate due to the characteristics of the sili-
con oscillator and varies by up to 30% over the temperature
and voltage range. By default, CCLK operates at approxi-
mately 6 MHz. Via the ConfigRate option, the oscillator fre-
quency is set at approximately 3, 6, 12, 25, or 50 MHz. At
power-on, CCLK always starts operation at its lowest fre-
quency. The device does not start operating at the higher
frequency until the ConfigRate control bits are loaded dur-
ing the configuration process.
DS099-4 (v1.5) July 13, 2004
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