XC3S50 Datasheet, PDF (58/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: DC and Switching Characteristics
I/O Timing
Table 12: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Max
Max Units
Clock-to-Output Times
T_ICKOFDCM
When reading from the
Output Flip-Flop (OFF), the
time from the active
transition on the Global
Clock pin to data appearing
at the Output pin. The DCM
is in use.
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew
rate, with DCM⁽³⁾
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
2.59
ns
2.59
ns
2.59
ns
2.59
ns
2.60
ns
2.60
ns
XC3S4000
2.60
ns
T_ICKOF
When reading from OFF, the
time from the active
transition on the Global
Clock pin to data appearing
at the Output pin. The DCM
is not in use.
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew
rate, without DCM
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
2.60
ns
5.37
ns
5.39
ns
5.42
ns
5.51
ns
5.65
ns
XC3S2000
5.83
ns
XC3S4000
5.95
ns
XC3S5000
6.19
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set
forth in Table 5 and Table 8.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock
Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true,
add the appropriate Input adjustment from Table 16. If the latter is true, add the appropriate Output adjustment from Table 19.
3. DCM output jitter is included in all measurements.
DS099-3 (v1.3) March 4, 2004
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