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R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 28: Switching Characteristics for the DLL
Symbol
Output Frequency Ranges
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_1X_HF
Description
Frequency Mode /
F_CLKIN Range
Frequency for the
CLK0, CLK90,
CLK180, and
CLK270 outputs
Frequency for the
CLK0 and CLK180
outputs
Low
High
CLKOUT_FREQ_2X_LF
Frequency for the
CLK2X and
CLK2X180 outputs
CLKOUT_FREQ_DV_LF
CLKOUT_FREQ_DV_HF
Frequency for the
CLKDV output
Output Clock Jitter
CLKOUT_PER_JITT_0
Period jitter at the
CLK0 output
CLKOUT_PER_JITT_90
Period jitter at the
CLK90 output
CLKOUT_PER_JITT_180
Period jitter at the
CLK180 output
CLKOUT_PER_JITT_270
Period jitter at the
CLK270 output
CLKOUT_PER_JITT_2X
Period jitter at the
CLK2X and
CLK2X180 outputs
CLKOUT_PER_JITT_DV1
Period jitter at the
CLKDV output
when performing
integer division
CLKOUT_PER_JITT_DV2
Period jitter at the
CLKDV output
when performing
non-integer
division
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL⁽⁴⁾
Duty cycle
variation for the
CLK0, CLK90,
CLK180, CLK270,
CLK2X,
CLK2X180, and
CLKDV outputs
Low
Low
High
All
All
Device
Revision
Speed Grade
-5
-4
Min Max Min Max Units
All
24 165 24 165 MHz
0 Nophase 48 280 48 280 MHz
shifting
Phase 48 200 48 200 MHz
shifting
Future
48 326 48 TBD MHz
0⁽³⁾
48 330 48 330 MHz
Future
48 330 48 330 MHz
All
1.5 100 1.5 100 MHz
All
3 215 3 215 MHz
All
-100 +100 -100 +100 ps
-150 +150 -150 +150 ps
-150 +150 -150 +150 ps
-150 +150 -150 +150 ps
-200 +200 -200 +200 ps
-150 +150 -150 +150 ps
-300 +300 -300 +300 ps
All
-150 +150 -150 +150 ps
DS099-3 (v1.3) March 4, 2004
www.xilinx.com
29
Advance Product Specification
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