XC3S50 Datasheet, PDF (122/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: Pinout Descriptions
Table 22: User I/Os Per Bank for XC3S200 and XC3S400 in PQ208 Package
Maximum
Package Edge I/O Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
16
9
0
2
3
Top
1
15
9
0
2
2
2
19
14
0
2
3
Right
3
20
15
0
2
3
4
17
4
6
2
3
Bottom
5
15
3
6
2
2
6
19
14
0
2
3
Left
7
20
15
0
2
3
GCLK
2
2
0
0
2
2
0
0
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
35
Product Specification
1-800-255-7778