XC3S50 Datasheet, PDF (61/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: DC and Switching Characteristics
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Table 15: Propagation Times for the IOB Input Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Max
Max
Units
Propagation Times
T_IOPI
The time it takes for data
to travel from the Input
pin to the IOB’s I output
with no input delay
programmed
T_IOPID
The time it takes for data
to travel from the Input
pin to the I output with the
Input delay programmed
LVCMOS25⁽²⁾,
IOBDELAY = NONE
LVCMOS25⁽²⁾,
IOBDELAY = IFD
All
XC3S50
XC3S200
XC3S400
1.05
1.20
ns
3.16
3.63
ns
3.79
4.35
ns
3.79
4.35
ns
XC3S1000
4.05
4.65
ns
XC3S1500
4.22
4.85
ns
XC3S2000
4.40
5.05
ns
XC3S4000
4.57
5.25
ns
XC3S5000
4.92
5.65
ns
T_IOPLI
The time it takes for data LVCMOS25⁽²⁾,
All
to travel from the Input IOBDELAY = NONE
pin through the IFF latch
to the I output with no
input delay programmed
1.55
1.78
ns
T_IOPLID
The time it takes for data LVCMOS25⁽²⁾,
to travel from the Input IOBDELAY = IFD
pin through the IFF latch
XC3S50
XC3S200
3.66
4.21
ns
4.29
4.93
ns
to the I output with the
XC3S400
4.29
4.93
ns
input delay programmed
XC3S1000
4.55
5.23
ns
XC3S1500
4.73
5.43
ns
XC3S2000
4.90
5.63
ns
XC3S4000
5.07
5.83
ns
XC3S5000
5.42
6.23
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set forth
in Table 5 and Table 8.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When
this is true, add the appropriate Input adjustment from Table 16.
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