XC3S50 Datasheet, PDF (83/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: DC and Switching Characteristics
R
PROG_B
(Input)
INIT_B
(Open-Drain)
CS_B
(Input)
RDWR_B
(Input)
CCLK
(Input/Output)
T_SMCCW
T_SMCSCC
T_SMDCC
T_SMCCD
T_SMCCCS
T_CCH
T_CCL
T_SMWCC
1/F_CCPAR
D0 - D7
(Inputs)
BUSY
(Output)
High-Z
Byte 0
Byte 1
T_SMCKBY
Byte n
T_SMCKBY
Byte n+1
BUSY
High-Z
Notes:
1. Switching RDWR_B High or Low while holding CS_B Low asynchronously aborts configuration.
Figure 7: Waveforms for Master and Slave Parallel Configuration
DS099-3_05_041103
Table 36: Timing for the Master and Slave Parallel Configuration Modes
Symbol
Description
Clock-to-Output Times
T_SMCKBY
The time from the rising transition on the CCLK pin to a
signal transition at the BUSY pin
Setup Times
T_SMDCC
The time from the setup of data at the D0-D7 pins to the
rising transition at the CCLK pin
T_SMCSCC
The time from the setup of a logic level at the CS_B pin to
the rising transition at the CCLK pin
T_SMCCW(2)
The time from the setup of a logic level at the RDWR_B pin
to the rising transition at the CCLK pin
Slave/Master
Slave
Both
All Speed Grades
Min
Max
-
12.0
10.0
-
10.0
-
10.0
-
Units
ns
ns
ns
ns
36
www.xilinx.com
DS099-3 (v1.3) March 4, 2004
1-800-255-7778
Advance Product Specification