XC3S50 Datasheet, PDF(171/192 Page) Xilinx, Inc – Revolutionary 90-nanometer process technology

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XC3S50 Datasheet, PDF (171/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Spartan-3 FPGA Family: Pinout Descriptions

FG1156: 1156-lead Fine-pitch Ball Grid

Array

The 1,156-lead fine-pitch ball grid array package, FG1156,

supports two different Spartan-3 devices, namely the

XC3S4000, and the XC3S5000. The XC3S2000, however,

has fewer I/O pins, which consequently results in 73 uncon-

nected pins on the FG1156 package, labeled as âN.C.â In

Table 37 and Figure 16, these unconnected pins are indi-

cated with a black diamond symbol (Â).

The XC3S5000 has a single unconnected package pin, ball

AK31, which is also unconnected for the XC3S4000.

All the package pins appear in Table 37 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

If there is a difference between the XC3S2000 and

XC3S5000 pinouts, then that difference is highlighted in

Table 37. If the table entry is shaded grey, then there is an

unconnected pin on the XC3S2000 that maps to a user-I/O

pin on the XC3S4000 and XC3S5000. If the table entry is

shaded tan, which only occurs on ball L29 in I/O Bank 2,

then the unconnected pin on XC3S4000 maps to a

VREF-type pin on the XC3S5000. If the other VREF_2 pins

all connect to a voltage reference to support a special I/O

standard, then also connect the N.C. pin on the XC3S4000

to the same VREF_2 voltage. This provides maximum flexi-

bility as you could potentially migrate a design from the

XC3S4000 to the XC3S5000 FPGA without changing the

printed circuit board.

Pinout Table

Table 37: FG1156 Package Pinout

Bank

XC3S4000

Pin Name

N.C. (Â)

XC3S5000

Pin Name

FG1156

Number

E17

G12

J11

K11

K13

K16

K17

L13

Type

I/O

Table 37: FG1156 Package Pinout (Continued)

Bank

XC3S4000

Pin Name

XC3S5000

Pin Name

FG1156

Number

Type

0 IO

L16

I/O

0 IO

L17

I/O

0 IO/VREF_0 IO/VREF_0

VREF

0 IO/VREF_0 IO/VREF_0

E10

VREF

0 IO/VREF_0 IO/VREF_0

J14

VREF

0 IO/VREF_0 IO/VREF_0

L15

VREF

0 IO_L01N_0/ IO_L01N_0/

DCI

VRP_0

0 IO_L01P_0/ IO_L01P_0/

DCI

VRN_0

0 IO_L02N_0 IO_L02N_0

I/O

0 IO_L02P_0 IO_L02P_0

I/O

0 IO_L03N_0 IO_L03N_0

I/O

0 IO_L03P_0 IO_L03P_0

I/O

0 IO_L04N_0 IO_L04N_0

I/O

0 IO_L04P_0 IO_L04P_0

I/O

0 IO_L05N_0 IO_L05N_0

I/O

0 IO_L05P_0/ IO_L05P_0/

VREF_0

VREF

0 IO_L06N_0 IO_L06N_0

I/O

0 IO_L06P_0 IO_L06P_0

I/O

0 IO_L07N_0 IO_L07N_0

I/O

0 IO_L07P_0 IO_L07P_0

I/O

0 IO_L08N_0 IO_L08N_0

I/O

0 IO_L08P_0 IO_L08P_0

I/O

0 IO_L09N_0 IO_L09N_0

J10

I/O

0 IO_L09P_0 IO_L09P_0

H10

I/O

0 IO_L10N_0 IO_L10N_0

G10

I/O

0 IO_L10P_0 IO_L10P_0

F10

I/O

0 IO_L11N_0 IO_L11N_0

L12

I/O

0 IO_L11P_0 IO_L11P_0

K12

I/O

0 IO_L12N_0 IO_L12N_0

J12

I/O

0 IO_L12P_0 IO_L12P_0

H12

I/O

0 IO_L13N_0 IO_L13N_0

F12

I/O

0 IO_L13P_0 IO_L13P_0

E12

I/O

0 IO_L14N_0 IO_L14N_0

D12

I/O

0 IO_L14P_0 IO_L14P_0

C12

I/O

0 IO_L15N_0 IO_L15N_0

B12

I/O

0 IO_L15P_0 IO_L15P_0

A12

I/O

0 IO_L16N_0 IO_L16N_0

H13

I/O

0 IO_L16P_0 IO_L16P_0

G13

I/O

0 IO_L17N_0 IO_L17N_0

D13

I/O

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DS099-4 (v1.5) July 13, 2004

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Product Specification

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