XC3S50 Datasheet, PDF (37/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 1.2V FPGA Family: Functional Description
R
BUFGMUX elements on the same side towards the
center of the die. At the center of the die, clock signals
reach the eight-line horizontal spine, which spans the
width of the die. In turn, the horizontal spine branches
out into a subsidiary clock interconnect that accesses
the CLBs.
2. The clock input of either DCM on the same side of the
die — top or bottom — as the BUFGMUX element in
use.
A Global clock input is placed in a design using either a
BUFGMUX element or the BUFG (Global Clock Buffer) ele-
ment. For the purpose of minimizing the dynamic power dis-
sipation of the clock network, the Xilinx development
software automatically disables all clock line segments that
a design does not use.
GCLK7
GCLK5
GCLK6
GCLK4
DCM
4
4
4 BUFGMUX
4
4
DCM
4
•
8
•
•
•
Array Dependent
•
•
8
8
8
Horizontal Spine
•
•
•
•
Array Dependent
DCM
•
•
4
4
4
4 BUFGMUX
4
4
GCLK2
GCLK0
GCLK3
GCLK1
Figure 18: Spartan-3 Clock Network (Top View)
DCM
DS099-2_18_070203
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www.xilinx.com
DS099-2 (v1.2) July 11, 2003
1-800-255-7778
Advance Product Specification
40