English
Language : 

XC3S50 Datasheet, PDF (68/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology
◁
R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 20: Test Methods for Timing Measurement at I/Os (Continued)
Inputs
Outputs
Inputs and
Outputs
VREF
VL
VH
RT
VT
VM
Signal Standard
(V)
(V)
(V)
(Ω)
(V)
(V)
LVCMOS18
-
0
1.8
1M
0
0.9
LVDCI_18
1M
0
LVDCI_DV2_18
1M
0
LVCMOS25
-
0
2.5
1M
0
1.25
LVDCI_25
1M
0
LVDCI_DV2_25
1M
0
LVCMOS33
-
0
3.3
1M
0
1.65
LVDCI_33
1M
0
LVDCI_DV2_33
1M
0
LVTTL
-
0
3.3
1M
0
1.4
PCI33_3 Rising
-
Note 2
Note 2
25
0
0.94
Falling
25
3.3
2.03
SSTL18_I
SSTL18_I_DCI
0.9
VREF - 0.5
VREF + 0.5
50
50
0.9
VREF
0.9
SSTL2_I
SSTL2_I_DCI
1.25
VREF - 0.75 VREF + 0.75
50
50
1.25
1.25
VREF
SSTL2_II
SSTL2_II_DCI
1.25
VREF - 0.75 VREF + 0.75
25
50
1.25
1.25
VREF
Differential
LDT_25
-
0.6 - 0.125 0.6 + 0.125
60
0.6
0.6
LVDS_25
-
1.2 - 0.125 1.2 + 0.125
50
1.2
1.2
LVDS_25_DCI
1M
0
BLVDS_25
-
1.2 - 0.125 1.2 + 0.125
1M
0
1.2
LVDSEXT_25
-
1.2 - 0.125 1.2 + 0.125
50
1.2
1.2
LVDSEXT_25_DCI
-
-
ULVDS_25
-
0.6 - 0.125 0.6 + 0.125
60
0.6
0.6
LVPECL_25
-
1.6 - 0.3
1.6 + 0.3
1M
0
1.6
RSDS_25
-
1.3 - 0.1
1.3 + 0.1
50
1.2
1.2
Notes:
1. Descriptions of the relevant symbols are as follows:
VREF -- The reference voltage for setting the input switching threshold
VM -- Voltage of measurement point on signal transition
VL -- Low-level test voltage at Input pin
VH -- High-level test voltage at Input pin
RT -- Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required
VT -- Termination voltage
CL -- Load capacitance at Output pin, which is 0 pF for all standards
2. According to the PCI specification.
DS099-3 (v1.3) March 4, 2004
www.xilinx.com
21
Advance Product Specification
1-800-255-7778
40
 ▷