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R
Spartan-3 1.2V FPGA Family: Functional Description
Table 9: Block RAM Port Signals (Continued)
Signal
Description
Port A
Signal
Name
Port B
Signal
Name
Direction
Function
Data Output
DOA
Bus
DOB
Output _{Basic data access occurs whenever WE is inactive. The DO}
outputs mirror the data stored in the addressed memory
location.
Data access with WE asserted is also possible if one of the
following two attributes is chosen: WRITE_FIRST accesses
data before the write takes place. READ_FIRST accesses data
after the write occurs.
A third attribute, NO_CHANGE, latches the DO outputs upon
the assertion of WE.
It is possible to configure a port’s total data path width (w) to be
1, 2, 4, 9, 18, or 36 bits. This selection applies to both the DI and
DO paths. See the DI signal description.
Parity Data
Output(s)
DOPA
DOPB
Output
Parity inputs represent additional bits included in the data input
path to support error detection. The number of parity bits "p"
included in the DI (same as for the DO bus) depends on a port’s
total data path width (w). See Table 10.
Write Enable
WEA
WEB
Input
When asserted together with EN, this input enables the writing
of data to the RAM. In this case, the data access attributes
WRITE_FIRST, READ_FIRST or NO_CHANGE determines if
and how data is updated on the DO outputs. See the DO signal
description.
When WE is inactive with EN asserted, read operations are still
possible. In this case, a transparent latch passes data from the
addressed memory location to the DO outputs.
Clock Enable
ENA
ENB
Input _{When asserted, this input enables the CLK signal to}
synchronize Block RAM functions as follows: the writing of data
to the DI inputs (when WE is also asserted), the updating of data
at the DO outputs as well as the setting/resetting of the DO
output latches.
When de-asserted, the above functions are disabled.
Set/Reset
SSRA
SSRB
Input
When asserted, this pin forces the DO output latch to the value
that the SRVAL attribute is set to. A Set/Reset operation on one
port has no effect on the other ports functioning, nor does it
disturb the memory’s data contents. It is synchronized to the
CLK signal.
Clock
CLKA
CLKB
Input
This input accepts the clock signal to which read and write
operations are synchronized. All associated port inputs are
required to meet setup times with respect to the clock signal’s
active edge. The data output bus responds after a clock-to-out
delay referenced to the clock signal’s active edge.
Port Aspect Ratios
On a given port, it is possible to select a number of different
possible widths (w – p) for the DI/DO buses as shown in
Table 10. These two buses always have the same width.
This data bus width selection is independent for each port. If
the data bus width of Port A differs from that of Port B, the
Block RAM automatically performs a bus-matching function.
When data are written to a port with a narrow bus, then read
from a port with a wide bus, the latter port will effectively
combine “narrow” words to form “wide” words. Similarly,
when data are written into a port with a wide bus, then read
from a port with a narrow bus, the latter port will divide
DS099-2 (v1.2) July 11, 2003
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